1/* 2 * (C) Copyright 2001, 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#include <mpc8xx_irq.h> 32 33 34# ifdef DEBUG 35# warning DEBUG Defined 36# endif /* DEBUG */ 37 38/* 39 * High Level Configuration Options 40 * (easy to change) 41 */ 42#define CONFIG_MPC860 1 43#define CONFIG_IAD210 1 /* ...on a IAD210 module */ 44#define CONFIG_MPC860T 1 45#define CONFIG_MPC862 1 46 47#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 48 49#undef CONFIG_8xx_CONS_SMC1 50#undef CONFIG_8xx_CONS_SMC2 51#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */ 52#undef CONFIG_8xx_CONS_NONE 53#define CONFIG_BAUDRATE 9600 54 55 56# define MPC8XX_FACT 16 57# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */ 58# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 59 60#if 0 61# define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 62#else 63# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 64#endif 65 66#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 67 68/* using this define saves us updating another source file */ 69#define CONFIG_BOARD_EARLY_INIT_F 1 70#define CONFIG_MISC_INIT_R 71 72#undef CONFIG_BOOTARGS 73/* #define CONFIG_BOOTCOMMAND \ 74 "bootp;" \ 75 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 76 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ 77 "bootm" 78*/ 79 80#define CONFIG_BOOTCOMMAND \ 81 "setenv bootargs root=/dev/nfs" \ 82 "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ 83 84#undef CONFIG_WATCHDOG /* watchdog disabled */ 85 86/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */ 87 88/* 89 * BOOTP options 90 */ 91#define CONFIG_BOOTP_SUBNETMASK 92#define CONFIG_BOOTP_GATEWAY 93#define CONFIG_BOOTP_HOSTNAME 94#define CONFIG_BOOTP_BOOTPATH 95#define CONFIG_BOOTP_BOOTFILESIZE 96 97 98# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ 99# define CONFIG_FEC_ENET 1 /* use FEC ethernet */ 100# define CONFIG_MII 1 101# define CONFIG_SYS_DISCOVER_PHY 1 102# define CONFIG_FEC_UTOPIA 1 103# define CONFIG_ETHADDR 08:00:06:26:A2:6D 104# define CONFIG_IPADDR 192.168.28.128 105# define CONFIG_SERVERIP 139.10.137.138 106# define CONFIG_SYS_DISCOVER_PHY 1 107 108#define CONFIG_MAC_PARTITION 109#define CONFIG_DOS_PARTITION 110 111/* enable I2C and select the hardware/software driver */ 112#undef CONFIG_HARD_I2C /* I2C with hardware support */ 113#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 114# define CONFIG_SYS_I2C_SPEED 50000 115# define CONFIG_SYS_I2C_SLAVE 0xDD 116# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 117/* 118 * Software (bit-bang) I2C driver configuration 119 */ 120#define PB_SCL 0x00000020 /* PB 26 */ 121#define PB_SDA 0x00000010 /* PB 27 */ 122 123#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 124#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 125#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 126#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 127#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 128 else immr->im_cpm.cp_pbdat &= ~PB_SDA 129#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 130 else immr->im_cpm.cp_pbdat &= ~PB_SCL 131#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 132 133#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 134 135 136/* 137 * Command line configuration. 138 */ 139#include <config_cmd_default.h> 140 141#define CONFIG_CMD_ASKENV 142#define CONFIG_CMD_DHCP 143#define CONFIG_CMD_DATE 144 145 146/* 147 * Miscellaneous configurable options 148 */ 149#define CONFIG_SYS_LONGHELP /* undef to save memory */ 150#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 151#if defined(CONFIG_CMD_KGDB) 152#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 153#else 154#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 155#endif 156#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 157#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 158#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 159 160#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 161#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ 162 163#define CONFIG_SYS_LOAD_ADDR 0x00100000 164 165#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 166 167#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 168 169/* 170 * Low Level Configuration Settings 171 * (address mappings, register initial values, etc.) 172 * You should know what you are doing if you make changes here. 173 */ 174/*----------------------------------------------------------------------- 175 * Internal Memory Mapped Register 176 */ 177#define CONFIG_SYS_IMMR 0xFFF00000 178#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) 179 180/*----------------------------------------------------------------------- 181 * Definitions for initial stack pointer and data area (in DPRAM) 182 */ 183#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 184#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 185#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 186#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 187#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 188 189/*----------------------------------------------------------------------- 190 * Start addresses for the final memory configuration 191 * (Set up by the startup code) 192 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 193 */ 194#define CONFIG_SYS_SDRAM_BASE 0x00000000 195#define CONFIG_SYS_FLASH_BASE 0x08000000 196#define CONFIG_SYS_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */ 197 198#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 199 200#if defined(DEBUG) 201# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 202#else 203# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 204#endif 205 206# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 207# define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 208 209/* 210 * For booting Linux, the board info and command line data 211 * have to be in the first 8 MB of memory, since this is 212 * the maximum mapped by the Linux kernel during initialization. 213 */ 214#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 215/*----------------------------------------------------------------------- 216 * FLASH organization 217 */ 218#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 219#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 220 221#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 222#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 223 224#define CONFIG_ENV_IS_IN_FLASH 1 225#define CONFIG_ENV_OFFSET 0x8000 226#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 227 228/*----------------------------------------------------------------------- 229 * Cache Configuration 230 */ 231#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 232#if defined(CONFIG_CMD_KGDB) 233#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 234#endif 235 236/*----------------------------------------------------------------------- 237 * SYPCR - System Protection Control 11-9 238 * SYPCR can only be written once after reset! 239 *----------------------------------------------------------------------- 240 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 241 */ 242#if defined(CONFIG_WATCHDOG) 243#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 244 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 245#else 246#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 247#endif 248 249/*----------------------------------------------------------------------- 250 * SIUMCR - SIU Module Configuration 11-6 251 *----------------------------------------------------------------------- 252 * PCMCIA config., multi-function pin tri-state 253 */ 254#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 255 256/*----------------------------------------------------------------------- 257 * TBSCR - Time Base Status and Control 11-26 258 *----------------------------------------------------------------------- 259 * Clear Reference Interrupt Status, Timebase freezing enabled 260 */ 261#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 262 263/*----------------------------------------------------------------------- 264 * PISCR - Periodic Interrupt Status and Control 11-31 265 *----------------------------------------------------------------------- 266 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 267 */ 268#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 269 270/*----------------------------------------------------------------------- 271 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 272 *----------------------------------------------------------------------- 273 * set the PLL, the low-power modes and the reset control (15-29) 274 */ 275#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ 276 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 277 278/*----------------------------------------------------------------------- 279 * SCCR - System Clock and reset Control Register 15-27 280 *----------------------------------------------------------------------- 281 * Set clock output, timebase and RTC source and divider, 282 * power management and some other internal clocks 283 */ 284#define SCCR_MASK SCCR_EBDF11 285 286#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ 287 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ 288 SCCR_DFLCD000 |SCCR_DFALCD00 ) 289 290/*----------------------------------------------------------------------- 291 * RCCR - RISC Controller Configuration Register 19-4 292 *----------------------------------------------------------------------- 293 */ 294/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ 295#define CONFIG_SYS_RCCR 0x0020 296 297/*----------------------------------------------------------------------- 298 * PCMCIA stuff 299 *----------------------------------------------------------------------- 300 */ 301#define PCMCIA_MEM_ADDR ((uint)0xff020000) 302#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) 303 304/*----------------------------------------------------------------------- 305 * 306 *----------------------------------------------------------------------- 307 * 308 */ 309#define CONFIG_SYS_DER 0 310 311/* Because of the way the 860 starts up and assigns CS0 the 312* entire address space, we have to set the memory controller 313* differently. Normally, you write the option register 314* first, and then enable the chip select by writing the 315* base register. For CS0, you must write the base register 316* first, followed by the option register. 317*/ 318 319/* 320 * Init Memory Controller: 321 * 322 * BR0 and OR0 (FLASH) 323 */ 324 325#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ 326 327/* used to re-map FLASH both when starting from SRAM or FLASH: 328 * restrict access enough to keep SRAM working (if any) 329 * but not too much to meddle with FLASH accesses 330 */ 331#define CONFIG_SYS_REMAP_OR_AM 0xF8000000 /* OR addr mask */ 332#define CONFIG_SYS_PRELIM_OR_AM 0xF8000000 /* OR addr mask */ 333 334/* FLASH timing: 335 TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ 336#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ 337 OR_SCY_3_CLK | OR_EHTR) 338 339#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 340#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 341 342/* 343 * BR2/3 and OR2/3 (SDRAM) 344 * 345 */ 346#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */ 347#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 348 349/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 350 351#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4) 352#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 353#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) 354 355/* 356 * Memory Periodic Timer Prescaler 357 */ 358 359/* periodic timer for refresh */ 360#define CONFIG_SYS_MAMR_PTA 124 /* start with divider for 64 MHz */ 361 362/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 363#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */ 364 365/* 366 * MAMR settings for SDRAM 367 */ 368 369#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 370 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 371 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X) 372 373 374/* 375 * Internal Definitions 376 * 377 * Boot Flags 378 */ 379#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 380#define BOOTFLAG_WARM 0x02 /* Software reboot */ 381 382#ifdef CONFIG_MPC860T 383 384/* Interrupt level assignments. 385*/ 386#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ 387 388#endif /* CONFIG_MPC860T */ 389 390 391#endif /* __CONFIG_H */ 392