1/* 2 * (C) Copyright 2003-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27/* 28 * High Level Configuration Options 29 * (easy to change) 30 */ 31 32#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 33#define CONFIG_ICECUBE 1 /* ... on IceCube board */ 34 35#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 36 37#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 38#define BOOTFLAG_WARM 0x02 /* Software reboot */ 39 40#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 41 42/* 43 * Serial console configuration 44 */ 45#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 46#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 47#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 48 49 50#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ 51/* 52 * PCI Mapping: 53 * 0x40000000 - 0x4fffffff - PCI Memory 54 * 0x50000000 - 0x50ffffff - PCI IO Space 55 */ 56#define CONFIG_PCI 57 58#if defined(CONFIG_PCI) 59#define CONFIG_PCI_PNP 1 60#define CONFIG_PCI_SCAN_SHOW 1 61#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 62 63#define CONFIG_PCI_MEM_BUS 0x40000000 64#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 65#define CONFIG_PCI_MEM_SIZE 0x10000000 66 67#define CONFIG_PCI_IO_BUS 0x50000000 68#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 69#define CONFIG_PCI_IO_SIZE 0x01000000 70#endif 71 72#define CONFIG_SYS_XLB_PIPELINING 1 73 74#define CONFIG_NET_MULTI 1 75#define CONFIG_MII 1 76#define CONFIG_EEPRO100 1 77#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 78#define CONFIG_NS8382X 1 79 80#else 81#define CONFIG_MII 1 82#endif 83 84/* Partitions */ 85#define CONFIG_MAC_PARTITION 86#define CONFIG_DOS_PARTITION 87#define CONFIG_ISO_PARTITION 88 89/* USB */ 90#define CONFIG_USB_OHCI_NEW 91#define CONFIG_USB_STORAGE 92#define CONFIG_SYS_OHCI_BE_CONTROLLER 93#undef CONFIG_SYS_USB_OHCI_BOARD_INIT 94#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 95#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB 96#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" 97#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 98 99#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 100 101 102/* 103 * BOOTP options 104 */ 105#define CONFIG_BOOTP_BOOTFILESIZE 106#define CONFIG_BOOTP_BOOTPATH 107#define CONFIG_BOOTP_GATEWAY 108#define CONFIG_BOOTP_HOSTNAME 109 110 111/* 112 * Command line configuration. 113 */ 114#include <config_cmd_default.h> 115 116#define CONFIG_CMD_EEPROM 117#define CONFIG_CMD_FAT 118#define CONFIG_CMD_I2C 119#define CONFIG_CMD_IDE 120#define CONFIG_CMD_NFS 121#define CONFIG_CMD_SNTP 122#define CONFIG_CMD_USB 123 124#if defined(CONFIG_PCI) 125#define CONFIG_CMD_PCI 126#endif 127 128 129#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ 130# define CONFIG_SYS_LOWBOOT 1 131# define CONFIG_SYS_LOWBOOT16 1 132#endif 133#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ 134#if defined(CONFIG_LITE5200B) 135# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B 136#else 137# define CONFIG_SYS_LOWBOOT 1 138# define CONFIG_SYS_LOWBOOT08 1 139#endif 140#endif 141 142/* 143 * Autobooting 144 */ 145#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 146 147#define CONFIG_PREBOOT "echo;" \ 148 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 149 "echo" 150 151#undef CONFIG_BOOTARGS 152 153#define CONFIG_EXTRA_ENV_SETTINGS \ 154 "netdev=eth0\0" \ 155 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 156 "nfsroot=${serverip}:${rootpath}\0" \ 157 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 158 "addip=setenv bootargs ${bootargs} " \ 159 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 160 ":${hostname}:${netdev}:off panic=1\0" \ 161 "flash_nfs=run nfsargs addip;" \ 162 "bootm ${kernel_addr}\0" \ 163 "flash_self=run ramargs addip;" \ 164 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 165 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 166 "rootpath=/opt/eldk/ppc_82xx\0" \ 167 "bootfile=/tftpboot/MPC5200/uImage\0" \ 168 "" 169 170#define CONFIG_BOOTCOMMAND "run flash_self" 171 172#if defined(CONFIG_MPC5200) 173/* 174 * IPB Bus clocking configuration. 175 */ 176#if defined(CONFIG_LITE5200B) 177#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 178#else 179#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 180#endif 181#endif /* CONFIG_MPC5200 */ 182 183/* pass open firmware flat tree */ 184#define CONFIG_OF_LIBFDT 1 185#define CONFIG_OF_BOARD_SETUP 1 186 187#define OF_CPU "PowerPC,5200@0" 188#define OF_SOC "soc5200@f0000000" 189#define OF_TBCLK (bd->bi_busfreq / 4) 190#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" 191 192/* 193 * I2C configuration 194 */ 195#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 196#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 197 198#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 199#define CONFIG_SYS_I2C_SLAVE 0x7F 200 201/* 202 * EEPROM configuration 203 */ 204#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 205#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 206#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 207#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 208 209/* 210 * Flash configuration 211 */ 212#if defined(CONFIG_LITE5200B) 213#define CONFIG_SYS_FLASH_BASE 0xFE000000 214#define CONFIG_SYS_FLASH_SIZE 0x01000000 215#if !defined(CONFIG_SYS_LOWBOOT) 216#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000) 217#else /* CONFIG_SYS_LOWBOOT */ 218#if defined(CONFIG_SYS_LOWBOOT08) 219# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B 220#endif 221#if defined(CONFIG_SYS_LOWBOOT16) 222#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000) 223#endif 224#endif /* CONFIG_SYS_LOWBOOT */ 225#else /* !CONFIG_LITE5200B (IceCube)*/ 226#define CONFIG_SYS_FLASH_BASE 0xFF000000 227#define CONFIG_SYS_FLASH_SIZE 0x01000000 228#if !defined(CONFIG_SYS_LOWBOOT) 229#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000) 230#else /* CONFIG_SYS_LOWBOOT */ 231#if defined(CONFIG_SYS_LOWBOOT08) 232#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000) 233#endif 234#if defined(CONFIG_SYS_LOWBOOT16) 235#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) 236#endif 237#endif /* CONFIG_SYS_LOWBOOT */ 238#endif /* CONFIG_LITE5200B */ 239#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ 240 241#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 242 243#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 244#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 245 246#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ 247 248#if defined(CONFIG_LITE5200B) 249#define CONFIG_FLASH_CFI_DRIVER 250#define CONFIG_SYS_FLASH_CFI 251#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START} 252#endif 253 254 255/* 256 * Environment settings 257 */ 258#define CONFIG_ENV_IS_IN_FLASH 1 259#define CONFIG_ENV_SIZE 0x10000 260#if defined(CONFIG_LITE5200B) 261#define CONFIG_ENV_SECT_SIZE 0x20000 262#else 263#define CONFIG_ENV_SECT_SIZE 0x10000 264#endif 265#define CONFIG_ENV_OVERWRITE 1 266 267/* 268 * Memory map 269 */ 270#define CONFIG_SYS_MBAR 0xF0000000 271#define CONFIG_SYS_SDRAM_BASE 0x00000000 272#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 273 274/* Use SRAM until RAM will be available */ 275#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 276#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ 277 278 279#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 280#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 281#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 282 283#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 284#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 285# define CONFIG_SYS_RAMBOOT 1 286#endif 287 288#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 289#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 290#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 291 292/* 293 * Ethernet configuration 294 */ 295#define CONFIG_MPC5xxx_FEC 1 296#define CONFIG_MPC5xxx_FEC_MII100 297/* 298 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb 299 */ 300/* #define CONFIG_MPC5xxx_FEC_MII10 */ 301#define CONFIG_PHY_ADDR 0x00 302 303/* 304 * GPIO configuration 305 */ 306#ifdef CONFIG_MPC5200_DDR 307#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004 308#else 309#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 310#endif 311 312/* 313 * Miscellaneous configurable options 314 */ 315#define CONFIG_SYS_LONGHELP /* undef to save memory */ 316#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 317#if defined(CONFIG_CMD_KGDB) 318#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 319#else 320#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 321#endif 322#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 323#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 324#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 325 326#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 327#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 328 329#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 330 331#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 332 333#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 334#if defined(CONFIG_CMD_KGDB) 335# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 336#endif 337 338/* 339 * Various low-level settings 340 */ 341#if defined(CONFIG_MPC5200) 342#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 343#define CONFIG_SYS_HID0_FINAL HID0_ICE 344#else 345#define CONFIG_SYS_HID0_INIT 0 346#define CONFIG_SYS_HID0_FINAL 0 347#endif 348 349#if defined(CONFIG_LITE5200B) 350#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE 351#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE 352#define CONFIG_SYS_CS1_CFG 0x00047800 353#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) 354#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 355#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START 356#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 357#define CONFIG_SYS_BOOTCS_CFG 0x00047800 358#else /* IceCube aka Lite5200 */ 359#ifdef CONFIG_MPC5200_DDR 360 361#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE) 362#define CONFIG_SYS_BOOTCS_SIZE 0x00800000 363#define CONFIG_SYS_BOOTCS_CFG 0x00047801 364#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE 365#define CONFIG_SYS_CS1_SIZE 0x00800000 366#define CONFIG_SYS_CS1_CFG 0x00047800 367 368#else /* !CONFIG_MPC5200_DDR */ 369 370#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 371#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 372#define CONFIG_SYS_BOOTCS_CFG 0x00047801 373#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 374#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 375 376#endif /* CONFIG_MPC5200_DDR */ 377#endif /*CONFIG_LITE5200B */ 378 379#define CONFIG_SYS_CS_BURST 0x00000000 380#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 381 382#define CONFIG_SYS_RESET_ADDRESS 0xff000000 383 384/*----------------------------------------------------------------------- 385 * USB stuff 386 *----------------------------------------------------------------------- 387 */ 388#define CONFIG_USB_CLOCK 0x0001BBBB 389#define CONFIG_USB_CONFIG 0x00001000 390 391/*----------------------------------------------------------------------- 392 * IDE/ATA stuff Supports IDE harddisk 393 *----------------------------------------------------------------------- 394 */ 395 396#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 397 398#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 399#undef CONFIG_IDE_LED /* LED for ide not supported */ 400 401#define CONFIG_IDE_RESET /* reset for ide supported */ 402#define CONFIG_IDE_PREINIT 403 404#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 405#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ 406 407#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 408 409#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 410 411/* Offset for data I/O */ 412#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 413 414/* Offset for normal register accesses */ 415#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 416 417/* Offset for alternate registers */ 418#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 419 420/* Interval between registers */ 421#define CONFIG_SYS_ATA_STRIDE 4 422 423#define CONFIG_ATAPI 1 424 425#endif /* __CONFIG_H */ 426