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27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32
33
34#define CONFIG_E300 1
35#define CONFIG_MPC83XX 1
36#define CONFIG_MPC834X 1
37#define CONFIG_MPC8349 1
38#define CONFIG_TQM834X 1
39
40
41#define CONFIG_SYS_IMMR 0xff400000
42
43
44#define CONFIG_83XX_CLKIN 66666000
45
46
47
48
49
50
51
52
53
54
55#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
56
57
58#undef CONFIG_BOARD_EARLY_INIT_F
59
60
61#define CONFIG_BOARD_EARLY_INIT_R
62
63
64
65
66#define CONFIG_SYS_DDR_BASE 0x00000000
67#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
68#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
69#define DDR_CASLAT_25
70#undef CONFIG_DDR_ECC
71#undef CONFIG_SPD_EEPROM
72
73#undef CONFIG_SYS_DRAM_TEST
74#define CONFIG_SYS_MEMTEST_START 0x00000000
75#define CONFIG_SYS_MEMTEST_END 0x00100000
76
77
78
79
80#define CONFIG_SYS_FLASH_CFI
81#define CONFIG_FLASH_CFI_DRIVER
82#undef CONFIG_SYS_FLASH_CHECKSUM
83#define CONFIG_SYS_FLASH_BASE 0x80000000
84#define CONFIG_SYS_FLASH_SIZE 8
85
86
87#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
104#ifndef __ASSEMBLY__
105extern int tqm834x_num_flash_banks;
106#endif
107#define CONFIG_SYS_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
108
109#define CONFIG_SYS_MAX_FLASH_SECT 512
110
111
112#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) | \
113 BR_MS_GPCM | BR_PS_32 | BR_V)
114
115
116#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
117 OR_GPCM_SCY_5 | OR_GPCM_TRLX)
118
119#define CONFIG_SYS_PRELIM_OR_AM 0xc0000000
120
121#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
122
123#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D
124
125#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
126
127
128#define CONFIG_SYS_BR1_PRELIM 0x00000000
129#define CONFIG_SYS_OR1_PRELIM 0x00000000
130#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
131#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
132
133#define CONFIG_SYS_BR2_PRELIM 0x00000000
134#define CONFIG_SYS_OR2_PRELIM 0x00000000
135#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
136#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
137
138#define CONFIG_SYS_BR3_PRELIM 0x00000000
139#define CONFIG_SYS_OR3_PRELIM 0x00000000
140#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
141#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
142
143
144
145
146#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
147
148#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
149#define CONFIG_SYS_RAMBOOT
150#else
151#undef CONFIG_SYS_RAMBOOT
152#endif
153
154#define CONFIG_SYS_INIT_RAM_LOCK 1
155#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
156#define CONFIG_SYS_INIT_RAM_END 0x1000
157
158#define CONFIG_SYS_GBL_DATA_SIZE 0x100
159#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
160#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
161
162#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
163#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
164
165
166
167
168#define CONFIG_CONS_INDEX 1
169#undef CONFIG_SERIAL_SOFTWARE_FIFO
170#define CONFIG_SYS_NS16550
171#define CONFIG_SYS_NS16550_SERIAL
172#define CONFIG_SYS_NS16550_REG_SIZE 1
173#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
174
175#define CONFIG_SYS_BAUDRATE_TABLE \
176 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
177
178#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
179#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
180
181
182
183
184#define CONFIG_HARD_I2C
185#undef CONFIG_SOFT_I2C
186#define CONFIG_FSL_I2C
187#define CONFIG_SYS_I2C_SPEED 400000
188#define CONFIG_SYS_I2C_SLAVE 0x7F
189#define CONFIG_SYS_I2C_OFFSET 0x3000
190
191
192#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
193#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
194#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
195#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
196#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
197
198
199#define CONFIG_RTC_DS1337
200#define CONFIG_SYS_I2C_RTC_ADDR 0x68
201
202
203#define CONFIG_DTT_LM75 1
204#define CONFIG_DTT_SENSORS {0}
205#define CONFIG_SYS_DTT_MAX_TEMP 70
206#define CONFIG_SYS_DTT_LOW_TEMP -30
207#define CONFIG_SYS_DTT_HYSTERESIS 3
208
209
210
211
212#define CONFIG_TSEC_ENET
213#define CONFIG_MII
214
215#define CONFIG_SYS_TSEC1_OFFSET 0x24000
216#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
217#define CONFIG_SYS_TSEC2_OFFSET 0x25000
218#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
219
220#if defined(CONFIG_TSEC_ENET)
221
222#ifndef CONFIG_NET_MULTI
223#define CONFIG_NET_MULTI
224#endif
225
226#define CONFIG_TSEC1 1
227#define CONFIG_TSEC1_NAME "TSEC0"
228#define CONFIG_TSEC2 1
229#define CONFIG_TSEC2_NAME "TSEC1"
230#define TSEC1_PHY_ADDR 2
231#define TSEC2_PHY_ADDR 1
232#define TSEC1_PHYIDX 0
233#define TSEC2_PHYIDX 0
234#define TSEC1_FLAGS TSEC_GIGABIT
235#define TSEC2_FLAGS TSEC_GIGABIT
236
237
238#define CONFIG_ETHPRIME "TSEC0"
239
240#endif
241
242
243
244
245
246#define CONFIG_PCI
247
248#if defined(CONFIG_PCI)
249
250#define CONFIG_PCI_PNP
251#define CONFIG_PCI_SCAN_SHOW
252
253
254#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000
255#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
256#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
257#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
258#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
259#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000
260
261#undef CONFIG_EEPRO100
262#define CONFIG_EEPRO100
263#undef CONFIG_TULIP
264
265#if !defined(CONFIG_PCI_PNP)
266 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
267 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
268 #define PCI_IDSEL_NUMBER 0x1c
269#endif
270
271#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
272
273#endif
274
275
276
277
278#define CONFIG_ENV_OVERWRITE
279
280#ifndef CONFIG_SYS_RAMBOOT
281 #define CONFIG_ENV_IS_IN_FLASH 1
282 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
283 #define CONFIG_ENV_SECT_SIZE 0x40000
284 #define CONFIG_ENV_SIZE 0x2000
285#else
286 #define CONFIG_SYS_NO_FLASH 1
287 #define CONFIG_ENV_IS_NOWHERE 1
288 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
289 #define CONFIG_ENV_SIZE 0x2000
290#endif
291
292#define CONFIG_LOADS_ECHO 1
293#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
294
295
296
297
298#define CONFIG_BOOTP_BOOTFILESIZE
299#define CONFIG_BOOTP_BOOTPATH
300#define CONFIG_BOOTP_GATEWAY
301#define CONFIG_BOOTP_HOSTNAME
302
303
304
305
306
307#include <config_cmd_default.h>
308
309#define CONFIG_CMD_DATE
310#define CONFIG_CMD_DTT
311#define CONFIG_CMD_EEPROM
312#define CONFIG_CMD_I2C
313#define CONFIG_CMD_JFFS2
314#define CONFIG_CMD_MII
315#define CONFIG_CMD_PING
316#define CONFIG_CMD_DHCP
317
318#if defined(CONFIG_PCI)
319 #define CONFIG_CMD_PCI
320#endif
321
322#if defined(CONFIG_SYS_RAMBOOT)
323 #undef CONFIG_CMD_SAVEENV
324 #undef CONFIG_CMD_LOADS
325#endif
326
327
328
329
330#define CONFIG_SYS_LONGHELP
331#define CONFIG_SYS_LOAD_ADDR 0x2000000
332#define CONFIG_SYS_PROMPT "=> "
333
334#define CONFIG_CMDLINE_EDITING 1
335#define CONFIG_SYS_HUSH_PARSER 1
336#ifdef CONFIG_SYS_HUSH_PARSER
337#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
338#endif
339
340#if defined(CONFIG_CMD_KGDB)
341 #define CONFIG_SYS_CBSIZE 1024
342#else
343 #define CONFIG_SYS_CBSIZE 256
344#endif
345
346#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
347#define CONFIG_SYS_MAXARGS 16
348#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
349#define CONFIG_SYS_HZ 1000
350
351#undef CONFIG_WATCHDOG
352
353
354
355
356
357
358#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
359
360#define CONFIG_SYS_HRCW_LOW (\
361 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
362 HRCWL_DDR_TO_SCB_CLK_1X1 |\
363 HRCWL_CSB_TO_CLKIN_4X1 |\
364 HRCWL_VCO_1X2 |\
365 HRCWL_CORE_TO_CSB_2X1)
366
367#if defined(PCI_64BIT)
368#define CONFIG_SYS_HRCW_HIGH (\
369 HRCWH_PCI_HOST |\
370 HRCWH_64_BIT_PCI |\
371 HRCWH_PCI1_ARBITER_ENABLE |\
372 HRCWH_PCI2_ARBITER_DISABLE |\
373 HRCWH_CORE_ENABLE |\
374 HRCWH_FROM_0X00000100 |\
375 HRCWH_BOOTSEQ_DISABLE |\
376 HRCWH_SW_WATCHDOG_DISABLE |\
377 HRCWH_ROM_LOC_LOCAL_16BIT |\
378 HRCWH_TSEC1M_IN_GMII |\
379 HRCWH_TSEC2M_IN_GMII )
380#else
381#define CONFIG_SYS_HRCW_HIGH (\
382 HRCWH_PCI_HOST |\
383 HRCWH_32_BIT_PCI |\
384 HRCWH_PCI1_ARBITER_ENABLE |\
385 HRCWH_PCI2_ARBITER_DISABLE |\
386 HRCWH_CORE_ENABLE |\
387 HRCWH_FROM_0X00000100 |\
388 HRCWH_BOOTSEQ_DISABLE |\
389 HRCWH_SW_WATCHDOG_DISABLE |\
390 HRCWH_ROM_LOC_LOCAL_16BIT |\
391 HRCWH_TSEC1M_IN_GMII |\
392 HRCWH_TSEC2M_IN_GMII )
393#endif
394
395
396#define CONFIG_SYS_SICRH 0
397#define CONFIG_SYS_SICRL SICRL_LDP_A
398
399
400#define CONFIG_SYS_HID0_INIT 0x000000000
401#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
402#define CONFIG_SYS_HID2 HID2_HBE
403
404#define CONFIG_HIGH_BATS 1
405
406
407#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
408#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
409#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
410#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
411
412
413#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
414#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
415
416
417#ifdef CONFIG_PCI
418#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
419#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
420#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
421#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
422#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
423#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
424#else
425#define CONFIG_SYS_IBAT3L (0)
426#define CONFIG_SYS_IBAT3U (0)
427#define CONFIG_SYS_IBAT4L (0)
428#define CONFIG_SYS_IBAT4U (0)
429#define CONFIG_SYS_IBAT5L (0)
430#define CONFIG_SYS_IBAT5U (0)
431#endif
432
433
434#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
435#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
436
437
438#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
439#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
440
441#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
442#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
443#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
444#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
445#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
446#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
447#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
448#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
449#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
450#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
451#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
452#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
453#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
454#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
455#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
456#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
457
458
459
460
461
462
463#define BOOTFLAG_COLD 0x01
464#define BOOTFLAG_WARM 0x02
465
466#if defined(CONFIG_CMD_KGDB)
467#define CONFIG_KGDB_BAUDRATE 230400
468#define CONFIG_KGDB_SER_INDEX 2
469#endif
470
471
472
473
474
475#define CONFIG_LOADADDR 400000
476
477#define CONFIG_BOOTDELAY 6
478#undef CONFIG_BOOTARGS
479
480#define CONFIG_BAUDRATE 115200
481
482#define CONFIG_PREBOOT "echo;" \
483 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
484 "echo"
485
486#undef CONFIG_BOOTARGS
487
488#define CONFIG_EXTRA_ENV_SETTINGS \
489 "netdev=eth0\0" \
490 "hostname=tqm834x\0" \
491 "nfsargs=setenv bootargs root=/dev/nfs rw " \
492 "nfsroot=${serverip}:${rootpath}\0" \
493 "ramargs=setenv bootargs root=/dev/ram rw\0" \
494 "addip=setenv bootargs ${bootargs} " \
495 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
496 ":${hostname}:${netdev}:off panic=1\0" \
497 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
498 "flash_nfs=run nfsargs addip addtty;" \
499 "bootm ${kernel_addr}\0" \
500 "flash_self=run ramargs addip addtty;" \
501 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
502 "net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;" \
503 "bootm\0" \
504 "rootpath=/opt/eldk/ppc_6xx\0" \
505 "bootfile=/tftpboot/tqm834x/uImage\0" \
506 "kernel_addr=80060000\0" \
507 "ramdisk_addr=80160000\0" \
508 "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0" \
509 "update=protect off 80000000 8003ffff; " \
510 "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
511 "upd=run load update\0" \
512 ""
513
514#define CONFIG_BOOTCOMMAND "run flash_self"
515
516
517
518
519
520#define CONFIG_CMD_MTDPARTS
521#define MTDIDS_DEFAULT "nor0=TQM834x-0"
522
523
524#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
525 "1m(kernel),2m(initrd),"\
526 "-(user);"\
527
528#endif
529