1/* 2 * (C) Copyright 2003-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2004 6 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27#ifndef __CONFIG_H 28#define __CONFIG_H 29 30/* 31 * Check valid setting of revision define. 32 * Total5100 and Total5200 Rev.1 are identical except for the processor. 33 */ 34#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) 35#error CONFIG_TOTAL5200_REV must be 1 or 2 36#endif 37 38/* 39 * High Level Configuration Options 40 * (easy to change) 41 */ 42 43#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 44#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ 45 46#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 47 48#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 49#define BOOTFLAG_WARM 0x02 /* Software reboot */ 50 51#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 52 53/* 54 * Serial console configuration 55 */ 56#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ 57#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 58#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 59 60/* 61 * Video console 62 */ 63#define CONFIG_VIDEO 64#define CONFIG_VIDEO_SED13806 65#define CONFIG_VIDEO_SED13806_16BPP 66 67#define CONFIG_CFB_CONSOLE 68#define CONFIG_VIDEO_LOGO 69/* #define CONFIG_VIDEO_BMP_LOGO */ 70#define CONFIG_CONSOLE_EXTRA_INFO 71#define CONFIG_VGA_AS_SINGLE_DEVICE 72#define CONFIG_VIDEO_SW_CURSOR 73#define CONFIG_SPLASH_SCREEN 74 75 76#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ 77/* 78 * PCI Mapping: 79 * 0x40000000 - 0x4fffffff - PCI Memory 80 * 0x50000000 - 0x50ffffff - PCI IO Space 81 */ 82#define CONFIG_PCI 1 83#define CONFIG_PCI_PNP 1 84#define CONFIG_PCI_SCAN_SHOW 1 85#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 86 87#define CONFIG_PCI_MEM_BUS 0x40000000 88#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 89#define CONFIG_PCI_MEM_SIZE 0x10000000 90 91#define CONFIG_PCI_IO_BUS 0x50000000 92#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 93#define CONFIG_PCI_IO_SIZE 0x01000000 94 95#define CONFIG_NET_MULTI 1 96#define CONFIG_MII 1 97#define CONFIG_EEPRO100 1 98#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 99#define CONFIG_NS8382X 1 100 101#else /* MGT5100 */ 102 103#define CONFIG_MII 1 104 105#endif 106 107/* Partitions */ 108#define CONFIG_MAC_PARTITION 109#define CONFIG_DOS_PARTITION 110 111/* USB */ 112#define CONFIG_USB_OHCI 113#define CONFIG_USB_STORAGE 114 115 116/* 117 * BOOTP options 118 */ 119#define CONFIG_BOOTP_BOOTFILESIZE 120#define CONFIG_BOOTP_BOOTPATH 121#define CONFIG_BOOTP_GATEWAY 122#define CONFIG_BOOTP_HOSTNAME 123 124 125/* 126 * Command line configuration. 127 */ 128#include <config_cmd_default.h> 129 130#if defined(CONFIG_MPC5200) 131 #define CONFIG_CMD_PCI 132#endif 133 134#define CONFIG_CMD_BMP 135#define CONFIG_CMD_EEPROM 136#define CONFIG_CMD_FAT 137#define CONFIG_CMD_I2C 138#define CONFIG_CMD_IDE 139#define CONFIG_CMD_PING 140#define CONFIG_CMD_USB 141 142 143#if (TEXT_BASE == 0xFE000000) /* Boot low */ 144# define CONFIG_SYS_LOWBOOT 1 145#endif 146 147/* 148 * Autobooting 149 */ 150#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 151 152#define CONFIG_PREBOOT \ 153 "setenv stdout serial;setenv stderr serial;" \ 154 "echo;" \ 155 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 156 "echo" 157 158#undef CONFIG_BOOTARGS 159 160#define CONFIG_EXTRA_ENV_SETTINGS \ 161 "netdev=eth0\0" \ 162 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 163 "nfsroot=${serverip}:${rootpath}\0" \ 164 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 165 "addip=setenv bootargs ${bootargs} " \ 166 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 167 ":${hostname}:${netdev}:off panic=1\0" \ 168 "flash_nfs=run nfsargs addip;" \ 169 "bootm ${kernel_addr}\0" \ 170 "flash_self=run ramargs addip;" \ 171 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 172 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 173 "rootpath=/opt/eldk/ppc_82xx\0" \ 174 "bootfile=/tftpboot/MPC5200/uImage\0" \ 175 "" 176 177#define CONFIG_BOOTCOMMAND "run flash_self" 178 179#if defined(CONFIG_MPC5200) 180/* 181 * IPB Bus clocking configuration. 182 */ 183#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 184#endif 185 186/* 187 * I2C configuration 188 */ 189#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 190#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ 191 192#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 193#define CONFIG_SYS_I2C_SLAVE 0x7F 194 195/* 196 * EEPROM configuration 197 */ 198#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 199#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 200#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 201#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 202 203/* 204 * Flash configuration 205 */ 206#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 207#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 208#if CONFIG_TOTAL5200_REV==2 209# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ 210# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START } 211#else 212# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 213# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } 214#endif 215#define CONFIG_SYS_FLASH_EMPTY_INFO 216#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 217 218#if CONFIG_TOTAL5200_REV==1 219# define CONFIG_SYS_FLASH_BASE 0xFE000000 220# define CONFIG_SYS_FLASH_SIZE 0x02000000 221#elif CONFIG_TOTAL5200_REV==2 222# define CONFIG_SYS_FLASH_BASE 0xFA000000 223# define CONFIG_SYS_FLASH_SIZE 0x06000000 224#endif /* CONFIG_TOTAL5200_REV */ 225 226#if defined(CONFIG_SYS_LOWBOOT) 227# define CONFIG_ENV_ADDR 0xFE040000 228#else /* CONFIG_SYS_LOWBOOT */ 229# define CONFIG_ENV_ADDR 0xFFF40000 230#endif /* CONFIG_SYS_LOWBOOT */ 231 232/* 233 * Environment settings 234 */ 235#define CONFIG_ENV_IS_IN_FLASH 1 236#define CONFIG_ENV_SIZE 0x40000 237#define CONFIG_ENV_SECT_SIZE 0x40000 238#define CONFIG_ENV_OVERWRITE 1 239 240/* 241 * Memory map 242 */ 243#define CONFIG_SYS_SDRAM_BASE 0x00000000 244#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 245#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */ 246#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */ 247#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */ 248#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */ 249 250/* Use SRAM until RAM will be available */ 251#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 252#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ 253 254#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 255#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 256#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 257 258#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 259#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 260# define CONFIG_SYS_RAMBOOT 1 261#endif 262 263#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 264#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 265#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 266 267/* 268 * Ethernet configuration 269 */ 270#define CONFIG_MPC5xxx_FEC 1 271#define CONFIG_MPC5xxx_FEC_SEVENWIRE 272/* dummy, 7-wire FEC does not have phy address */ 273#define CONFIG_PHY_ADDR 0x00 274 275/* 276 * GPIO configuration 277 * 278 * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 279 * Reserved 0 280 * ALTs: CAN1/2 on PSC2, SPI on PSC3 00 281 * CS7: Interrupt GPIO on PSC3_5 0 282 * CS8: Interrupt GPIO on PSC3_4 0 283 * ATA: reset default, changed in ATA driver 00 284 * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 285 * IRDA: reset default, changed in IrDA driver 000 286 * ETHER: reset default, changed in Ethernet driver 0000 287 * PCI_DIS: reset default, changed in PCI driver 0 288 * USB_SE: reset default, changed in USB driver 0 289 * USB: reset default, changed in USB driver 00 290 * PSC3: SPI and UART functionality without CD 1100 291 * Reserved 0 292 * PSC2: CAN1/2 001 293 * Reserved 0 294 * PSC1: reset default, changed in AC'97 driver 000 295 * 296 */ 297#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10 298 299/* 300 * Miscellaneous configurable options 301 */ 302#define CONFIG_SYS_LONGHELP /* undef to save memory */ 303#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 304#if defined(CONFIG_CMD_KGDB) 305#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 306#else 307#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 308#endif 309#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 310#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 311#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 312 313#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 314#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 315 316#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 317 318#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 319 320#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 321#if defined(CONFIG_CMD_KGDB) 322# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 323#endif 324 325 326/* 327 * Various low-level settings 328 */ 329#if defined(CONFIG_MPC5200) 330#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 331#define CONFIG_SYS_HID0_FINAL HID0_ICE 332#else 333#define CONFIG_SYS_HID0_INIT 0 334#define CONFIG_SYS_HID0_FINAL 0 335#endif 336 337#if defined (CONFIG_MGT5100) 338# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */ 339#endif 340 341#if CONFIG_TOTAL5200_REV==1 342# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 343# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ 344# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ 345# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 346# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */ 347#else 348# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE) 349# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */ 350# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ 351# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE) 352# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */ 353# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ 354# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE 355# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */ 356# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ 357#endif 358 359#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE 360#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */ 361#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ 362 363#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE 364#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */ 365#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ 366 367#if CONFIG_TOTAL5200_REV==1 368# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE 369# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ 370# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ 371#else 372# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE 373# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */ 374# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ 375#endif 376 377#define CONFIG_SYS_CS_BURST 0x00000000 378#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 379 380/*----------------------------------------------------------------------- 381 * USB stuff 382 *----------------------------------------------------------------------- 383 */ 384#define CONFIG_USB_CLOCK 0x0001BBBB 385#define CONFIG_USB_CONFIG 0x00001000 386 387/*----------------------------------------------------------------------- 388 * IDE/ATA stuff Supports IDE harddisk 389 *----------------------------------------------------------------------- 390 */ 391 392#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 393 394#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 395#undef CONFIG_IDE_LED /* LED for ide not supported */ 396 397#define CONFIG_IDE_RESET /* reset for ide supported */ 398#define CONFIG_IDE_PREINIT 399 400#define CONFIG_SYS_ATA_CS_ON_I2C2 401#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 402#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 403 404#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 405 406#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 407 408/* Offset for data I/O */ 409#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 410 411/* Offset for normal register accesses */ 412#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 413 414/* Offset for alternate registers */ 415#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 416 417/* Interval between registers */ 418#define CONFIG_SYS_ATA_STRIDE 4 419 420#endif /* __CONFIG_H */ 421