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28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32
33
34
35
36#define CONFIG_405EP 1
37#define CONFIG_4xx 1
38#define CONFIG_VOH405 1
39
40#define CONFIG_BOARD_EARLY_INIT_F 1
41#define CONFIG_MISC_INIT_R 1
42
43#define CONFIG_SYS_CLK_FREQ 33333400
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3
47
48#undef CONFIG_BOOTARGS
49#undef CONFIG_BOOTCOMMAND
50
51#define CONFIG_PREBOOT
52
53#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
54
55#define CONFIG_NET_MULTI 1
56#undef CONFIG_HAS_ETH1
57
58#define CONFIG_PPC4xx_EMAC
59#define CONFIG_MII 1
60#define CONFIG_PHY_ADDR 0
61#define CONFIG_LXT971_NO_SLEEP 1
62#define CONFIG_RESET_PHY_R 1
63
64#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
65
66
67
68
69
70#define CONFIG_BOOTP_BOOTFILESIZE
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
74
75
76
77
78
79#include <config_cmd_default.h>
80
81#define CONFIG_CMD_DHCP
82#define CONFIG_CMD_PCI
83#define CONFIG_CMD_IRQ
84#define CONFIG_CMD_IDE
85#define CONFIG_CMD_FAT
86#define CONFIG_CMD_ELF
87#define CONFIG_CMD_NAND
88#define CONFIG_CMD_DATE
89#define CONFIG_CMD_I2C
90#define CONFIG_CMD_MII
91#define CONFIG_CMD_PING
92#define CONFIG_CMD_EEPROM
93
94
95#define CONFIG_MAC_PARTITION
96#define CONFIG_DOS_PARTITION
97
98#define CONFIG_SUPPORT_VFAT
99
100#undef CONFIG_WATCHDOG
101
102#define CONFIG_RTC_MC146818
103#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500
104
105#define CONFIG_SDRAM_BANK0 1
106
107
108
109
110#define CONFIG_SYS_LONGHELP
111#define CONFIG_SYS_PROMPT "=> "
112
113#undef CONFIG_SYS_HUSH_PARSER
114#ifdef CONFIG_SYS_HUSH_PARSER
115#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
116#endif
117
118#if defined(CONFIG_CMD_KGDB)
119#define CONFIG_SYS_CBSIZE 1024
120#else
121#define CONFIG_SYS_CBSIZE 256
122#endif
123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
124#define CONFIG_SYS_MAXARGS 16
125#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
126
127#define CONFIG_SYS_DEVICE_NULLDEV 1
128
129#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
130
131#define CONFIG_AUTO_COMPLETE 1
132
133#define CONFIG_SYS_MEMTEST_START 0x0400000
134#define CONFIG_SYS_MEMTEST_END 0x0C00000
135
136#undef CONFIG_SYS_EXT_SERIAL_CLOCK
137#define CONFIG_SYS_BASE_BAUD 691200
138#define CONFIG_UART1_CONSOLE
139
140
141#define CONFIG_SYS_BAUDRATE_TABLE \
142 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
143 57600, 115200, 230400, 460800, 921600 }
144
145#define CONFIG_SYS_LOAD_ADDR 0x100000
146#define CONFIG_SYS_EXTBDINFO 1
147
148#define CONFIG_SYS_HZ 1000
149
150#define CONFIG_ZERO_BOOTDELAY_CHECK
151
152#define CONFIG_VERSION_VARIABLE 1
153
154#define CONFIG_SYS_RX_ETH_BUFFER 16
155
156
157
158
159
160#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
161#define CONFIG_SYS_MAX_NAND_DEVICE 1
162#define NAND_BIG_DELAY_US 25
163
164#define CONFIG_SYS_NAND_CE (0x80000000 >> 1)
165#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)
166#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)
167#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)
168
169#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1
170#define CONFIG_SYS_NAND_QUIET 1
171
172
173
174
175
176#define PCI_HOST_ADAPTER 0
177#define PCI_HOST_FORCE 1
178#define PCI_HOST_AUTO 2
179
180#define CONFIG_PCI
181#define CONFIG_PCI_HOST PCI_HOST_HOST
182#define CONFIG_PCI_PNP
183
184
185#define CONFIG_PCI_SCAN_SHOW
186
187#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
188
189#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
190#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
191#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
192#define CONFIG_SYS_PCI_PTM1LA 0x00000000
193#define CONFIG_SYS_PCI_PTM1MS 0xfc000001
194#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
195#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
196#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
197#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
198
199
200
201
202
203#undef CONFIG_IDE_8xx_DIRECT
204#undef CONFIG_IDE_LED
205#define CONFIG_IDE_RESET 1
206
207#define CONFIG_SYS_IDE_MAXBUS 2
208#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2)
209
210#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
211#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
212#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0010
213
214#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
215#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
216#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
217
218
219
220
221
222
223#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
224
225
226
227#define FLASH_BASE0_PRELIM 0xFFC00000
228
229#define CONFIG_SYS_MAX_FLASH_BANKS 1
230#define CONFIG_SYS_MAX_FLASH_SECT 256
231
232#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
233#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
234
235#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
236#define CONFIG_SYS_FLASH_ADDR0 0x5555
237#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
238
239
240
241
242#define CONFIG_SYS_FLASH_READ0 0x0000
243#define CONFIG_SYS_FLASH_READ1 0x0001
244#define CONFIG_SYS_FLASH_READ2 0x0002
245
246#define CONFIG_SYS_FLASH_EMPTY_INFO
247
248
249
250
251
252
253#define CONFIG_SYS_SDRAM_BASE 0x00000000
254#define CONFIG_SYS_FLASH_BASE 0xFFF80000
255#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
256#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
257#define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024)
258
259#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
260# define CONFIG_SYS_RAMBOOT 1
261#else
262# undef CONFIG_SYS_RAMBOOT
263#endif
264
265
266
267
268#define CONFIG_ENV_IS_IN_EEPROM 1
269#define CONFIG_ENV_OFFSET 0x100
270#define CONFIG_ENV_SIZE 0x700
271
272
273#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500
274#define CONFIG_SYS_NVRAM_SIZE 242
275
276
277
278
279#define CONFIG_HARD_I2C
280#define CONFIG_SYS_I2C_SPEED 100000
281#define CONFIG_SYS_I2C_SLAVE 0x7F
282
283#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
284#define CONFIG_SYS_EEPROM_WREN 1
285
286
287#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
288
289#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
290#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
291
292
293#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
294
295
296
297
298
299#define CAN_BA 0xF0000000
300#define DUART0_BA 0xF0000400
301#define DUART1_BA 0xF0000408
302#define RTC_BA 0xF0000500
303#define VGA_BA 0xF1000000
304#define CONFIG_SYS_NAND_BASE 0xF4000000
305
306
307#define CONFIG_SYS_EBC_PB0AP 0x92015480
308
309#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
310
311
312#define CONFIG_SYS_EBC_PB1AP 0x92015480
313#define CONFIG_SYS_EBC_PB1CR 0xF4018000
314
315
316#define CONFIG_SYS_EBC_PB2AP 0x010053C0
317#define CONFIG_SYS_EBC_PB2CR 0xF0018000
318
319
320#define CONFIG_SYS_EBC_PB3AP 0x010053C0
321#define CONFIG_SYS_EBC_PB3CR 0xF011A000
322
323
324#define CONFIG_SYS_EBC_PB4AP 0x03805380
325#define CONFIG_SYS_EBC_PB4CR VGA_BA | 0x7A000
326
327
328
329
330
331#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000
332#define CONFIG_SYS_LCD_BIG_REG 0xF1000000
333#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000
334#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0
335
336#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
337
338
339
340
341
342#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100
343
344
345#define CONFIG_SYS_FPGA_CTRL 0x000
346
347
348#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
349#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
350#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
351
352#define CONFIG_SYS_FPGA_SPARTAN2 1
353#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024
354
355
356#define CONFIG_SYS_FPGA_PRG 0x04000000
357#define CONFIG_SYS_FPGA_CLK 0x02000000
358#define CONFIG_SYS_FPGA_DATA 0x01000000
359#define CONFIG_SYS_FPGA_INIT 0x00010000
360#define CONFIG_SYS_FPGA_DONE 0x00008000
361
362
363
364
365
366#define CONFIG_SYS_TEMP_STACK_OCM 1
367
368
369#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
370#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
371#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
372#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
373
374#define CONFIG_SYS_GBL_DATA_SIZE 128
375#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
376#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
377
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387
388
389
390#define CONFIG_SYS_GPIO0_OSRH 0x00000550
391#define CONFIG_SYS_GPIO0_OSRL 0x00000110
392#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
393#define CONFIG_SYS_GPIO0_ISR1L 0x15555440
394#define CONFIG_SYS_GPIO0_TSRH 0x00000000
395#define CONFIG_SYS_GPIO0_TSRL 0x00000000
396#define CONFIG_SYS_GPIO0_TCR 0x777E0017
397
398#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
399#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
400#define CONFIG_SYS_IIC_ON (0x80000000 >> 8)
401#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
402#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
403#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
404
405
406
407
408
409
410#define BOOTFLAG_COLD 0x01
411#define BOOTFLAG_WARM 0x02
412
413
414
415
416
417#if 1
418#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
419#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
420#endif
421#if 0
422#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
423#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
424#endif
425#if 0
426#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
427#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
428#endif
429
430#endif
431