1/* 2 * (C) Copyright 2001 3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ 37#define CONFIG_4xx 1 /* ...member of PPC405 family */ 38#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ 39#define CONFIG_W7OLMC 1 /* ...specifically an LMC */ 40 41#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 42#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ 43 44#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 45 46#define CONFIG_BAUDRATE 9600 47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 48 49#if 1 50#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ 51#else 52#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ 53#endif 54 55#undef CONFIG_BOOTARGS 56 57#define CONFIG_LOADADDR F0080000 58 59#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ 60#define CONFIG_OVERWRITE_ETHADDR_ONCE 61#define CONFIG_IPADDR 192.168.1.1 62#define CONFIG_NETMASK 255.255.255.0 63#define CONFIG_SERVERIP 192.168.1.2 64 65#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 66#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */ 67 68#define CONFIG_PPC4xx_EMAC 69#define CONFIG_MII 1 /* MII PHY management */ 70#define CONFIG_PHY_ADDR 0 /* PHY address */ 71 72#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ 73 74/* 75 * BOOTP options 76 */ 77#define CONFIG_BOOTP_BOOTFILESIZE 78#define CONFIG_BOOTP_BOOTPATH 79#define CONFIG_BOOTP_GATEWAY 80#define CONFIG_BOOTP_HOSTNAME 81 82 83/* 84 * Command line configuration. 85 */ 86#include <config_cmd_default.h> 87 88#define CONFIG_CMD_PCI 89#define CONFIG_CMD_IRQ 90#define CONFIG_CMD_ASKENV 91#define CONFIG_CMD_DHCP 92#define CONFIG_CMD_BEDBUG 93#define CONFIG_CMD_DATE 94#define CONFIG_CMD_I2C 95#define CONFIG_CMD_EEPROM 96#define CONFIG_CMD_ELF 97#define CONFIG_CMD_BSP 98#define CONFIG_CMD_REGINFO 99 100#undef CONFIG_WATCHDOG /* watchdog disabled */ 101#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ 102 103#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ 104#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ 105/* 106 * Miscellaneous configurable options 107 */ 108#define CONFIG_SYS_LONGHELP /* undef to save memory */ 109#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ 110#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */ 111#ifdef CONFIG_SYS_HUSH_PARSER 112#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 113#endif 114#if defined(CONFIG_CMD_KGDB) 115#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 116#else 117#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 118#endif 119#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 120#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 121#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 122 123#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 124#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 125 126#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ 127#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ 128#define CONFIG_SYS_BASE_BAUD 384000 129 130 131/* The following table includes the supported baudrates */ 132#define CONFIG_SYS_BAUDRATE_TABLE {9600} 133 134#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 135#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ 136 137#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 138 139/*----------------------------------------------------------------------- 140 * PCI stuff 141 *----------------------------------------------------------------------- 142 */ 143#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 144#define PCI_HOST_FORCE 1 /* configure as pci host */ 145#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 146 147 148#define CONFIG_PCI /* include pci support */ 149#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ 150#define CONFIG_PCI_PNP /* pci plug-and-play */ 151/* resource configuration */ 152#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ 153#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ 154#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 155#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ 156#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 157#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ 158#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ 159#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ 160 161/*----------------------------------------------------------------------- 162 * Set up values for external bus controller 163 * used by cpu_init.c 164 *----------------------------------------------------------------------- 165 */ 166 /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */ 167#undef CONFIG_USE_PERWE 168 169/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ 170#define CONFIG_SYS_TEMP_STACK_OCM 1 171 172/* bank 0 is boot flash */ 173/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ 174#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440 175/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ 176#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000 177 178/* bank 1 is main flash */ 179/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ 180#define CONFIG_SYS_EBC_PB1AP 0x05850240 181/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ 182#define CONFIG_SYS_EBC_PB1CR 0xF00FC000 183 184/* bank 2 is RTC/NVRAM */ 185/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ 186#define CONFIG_SYS_EBC_PB2AP 0x03000440 187/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ 188#define CONFIG_SYS_EBC_PB2CR 0xFC018000 189 190/* bank 3 is FPGA 0 */ 191/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ 192#define CONFIG_SYS_EBC_PB3AP 0x02000400 193/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ 194#define CONFIG_SYS_EBC_PB3CR 0xFD01A000 195 196/* bank 4 is FPGA 1 */ 197/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ 198#define CONFIG_SYS_EBC_PB4AP 0x02000400 199/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ 200#define CONFIG_SYS_EBC_PB4CR 0xFD11A000 201 202/* bank 5 is FPGA 2 */ 203/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ 204#define CONFIG_SYS_EBC_PB5AP 0x02000400 205/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ 206#define CONFIG_SYS_EBC_PB5CR 0xFD21A000 207 208/* bank 6 is unused */ 209/* pb6ap = 0 */ 210#define CONFIG_SYS_EBC_PB6AP 0x00000000 211/* pb6cr = 0 */ 212#define CONFIG_SYS_EBC_PB6CR 0x00000000 213 214/* bank 7 is LED register */ 215/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ 216#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440 217/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ 218#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000 219 220/*----------------------------------------------------------------------- 221 * Start addresses for the final memory configuration 222 * (Set up by the startup code) 223 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 224 */ 225#define CONFIG_SYS_SDRAM_BASE 0x00000000 226#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 227#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 228#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 229#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 230 231/* 232 * For booting Linux, the board info and command line data 233 * have to be in the first 8 MB of memory, since this is 234 * the maximum mapped by the Linux kernel during initialization. 235 */ 236#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 237/*----------------------------------------------------------------------- 238 * FLASH organization 239 */ 240#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 241#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ 242 243#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ 244#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ 245#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */ 246 247#if 1 /* Use NVRAM for environment variables */ 248/*----------------------------------------------------------------------- 249 * NVRAM organization 250 */ 251#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ 252#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ 253#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ 254#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ 255/*define CONFIG_ENV_ADDR \ 256 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */ 257#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR 258 259#else /* Use Boot Flash for environment variables */ 260/*----------------------------------------------------------------------- 261 * Flash EEPROM for environment 262 */ 263#define CONFIG_ENV_IS_IN_FLASH 1 264#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ 265#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */ 266 267#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ 268#endif 269 270/*----------------------------------------------------------------------- 271 * I2C EEPROM (CAT24WC08) for environment 272 */ 273#define CONFIG_HARD_I2C /* I2c with hardware support */ 274#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 275#define CONFIG_SYS_I2C_SLAVE 0x7F 276 277#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 278#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 279/* mask of address bits that overflow into the "EEPROM chip address" */ 280#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 281#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 282 /* 16 byte page write mode using*/ 283 /* last 4 bits of the address */ 284#define CONFIG_SYS_I2C_MULTI_EEPROMS 285/*----------------------------------------------------------------------- 286 * Definitions for Serial Presence Detect EEPROM address 287 * (to get SDRAM settings) 288 */ 289#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ 290 291/* 292 * Init Memory Controller: 293 */ 294#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ 295#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ 296 297/* On Chip Memory location */ 298#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 299#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 300 301/*----------------------------------------------------------------------- 302 * Definitions for initial stack pointer and data area (in RAM) 303 */ 304#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ 305#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ 306#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 307#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 308#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 309 310 311/* 312 * Internal Definitions 313 * 314 * Boot Flags 315 */ 316#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 317#define BOOTFLAG_WARM 0x02 /* Software reboot */ 318 319#if defined(CONFIG_CMD_KGDB) 320#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 321#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 322#endif 323 324/* 325 * FPGA(s) configuration 326 */ 327#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ 328#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */ 329#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ 330#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ 331#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ 332 333#endif /* __CONFIG_H */ 334