1/* 2 * (C) Copyright 2003-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2005-2007 6 * Modified for InterControl digsyMTC MPC5200 board by 7 * Frank Bodammer, GCD Hard- & Software GmbH, 8 * frank.bodammer@gcd-solutions.de 9 * 10 * (C) Copyright 2009 Semihalf 11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software\; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation\; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY\; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program\; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#ifndef __CONFIG_H 33#define __CONFIG_H 34 35/* 36 * High Level Configuration Options 37 */ 38 39#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 40#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ 41#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ 42 43#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 44 45#define BOOTFLAG_COLD 0x01 46#define BOOTFLAG_WARM 0x02 47 48#define CONFIG_SYS_CACHELINE_SIZE 32 49 50/* 51 * Serial console configuration 52 */ 53#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */ 54#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 55#define CONFIG_SYS_BAUDRATE_TABLE \ 56 { 9600, 19200, 38400, 57600, 115200, 230400 } 57 58/* 59 * PCI Mapping: 60 * 0x40000000 - 0x4fffffff - PCI Memory 61 * 0x50000000 - 0x50ffffff - PCI IO Space 62 */ 63#define CONFIG_PCI 1 64#define CONFIG_PCI_PNP 1 65#define CONFIG_PCI_SCAN_SHOW 1 66 67#define CONFIG_PCI_MEM_BUS 0x40000000 68#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 69#define CONFIG_PCI_MEM_SIZE 0x10000000 70 71#define CONFIG_PCI_IO_BUS 0x50000000 72#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 73#define CONFIG_PCI_IO_SIZE 0x01000000 74 75/* 76 * Partitions 77 */ 78#define CONFIG_DOS_PARTITION 79#define CONFIG_BZIP2 80 81/* 82 * Command line configuration. 83 */ 84#include <config_cmd_default.h> 85 86#define CONFIG_CMD_DFL 87#define CONFIG_CMD_CACHE 88#define CONFIG_CMD_DATE 89#define CONFIG_CMD_DHCP 90#define CONFIG_CMD_DIAG 91#define CONFIG_CMD_EEPROM 92#define CONFIG_CMD_ELF 93#define CONFIG_CMD_EXT2 94#define CONFIG_CMD_FAT 95#define CONFIG_CMD_I2C 96#define CONFIG_CMD_IDE 97#define CONFIG_CMD_IRQ 98#define CONFIG_CMD_MII 99#define CONFIG_CMD_PCI 100#define CONFIG_CMD_PING 101#define CONFIG_CMD_REGINFO 102#define CONFIG_CMD_SAVES 103#define CONFIG_CMD_USB 104 105#if (TEXT_BASE == 0xFF000000) 106#define CONFIG_SYS_LOWBOOT 1 107#endif 108 109/* 110 * Autobooting 111 */ 112#define CONFIG_BOOTDELAY 1 113 114#undef CONFIG_BOOTARGS 115 116#define CONFIG_EXTRA_ENV_SETTINGS \ 117 "netdev=eth0\0" \ 118 "console=ttyPSC0\0" \ 119 "kernel_addr_r=400000\0" \ 120 "fdt_addr_r=600000\0" \ 121 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 122 "nfsroot=${serverip}:${rootpath}\0" \ 123 "addip=setenv bootargs ${bootargs} " \ 124 "ip=${ipaddr}:${serverip}:${gatewayip}:"\ 125 "${netmask}:${hostname}:${netdev}:off panic=1\0" \ 126 "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\ 127 "rootpath=/opt/eldk/ppc_6xx\0" \ 128 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 129 "tftp ${fdt_addr_r} ${fdt_file};" \ 130 "run nfsargs addip addcons;" \ 131 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 132 "load=tftp 200000 ${u-boot}\0" \ 133 "update=protect off FFF00000 +${filesize};" \ 134 "erase FFF00000 +${filesize};" \ 135 "cp.b 200000 FFF00000 ${filesize};" \ 136 "protect on FFF00000 +${filesize}\0" \ 137 "" 138 139/* 140 * I2C configuration 141 */ 142#define CONFIG_HARD_I2C 1 143#define CONFIG_SYS_I2C_MODULE 1 144#define CONFIG_SYS_I2C_SPEED 100000 145#define CONFIG_SYS_I2C_SLAVE 0x7F 146 147/* 148 * EEPROM configuration 149 */ 150#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 151#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 152#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 153#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 154 155/* 156 * RTC configuration 157 */ 158#define CONFIG_RTC_DS1337 159#define CONFIG_SYS_I2C_RTC_ADDR 0x68 160 161/* 162 * Flash configuration 163 */ 164#define CONFIG_SYS_FLASH_CFI 1 165#define CONFIG_FLASH_CFI_DRIVER 1 166 167#define CONFIG_SYS_FLASH_BASE 0xFF000000 168#define CONFIG_SYS_FLASH_SIZE 0x01000000 169 170#define CONFIG_SYS_MAX_FLASH_BANKS 1 171#define CONFIG_SYS_MAX_FLASH_SECT 256 172#define CONFIG_FLASH_16BIT 173#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 174#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 175#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 176#define CONFIG_SYS_FLASH_WRITE_TOUT 500 177 178#define CONFIG_OF_LIBFDT 1 179#define CONFIG_OF_BOARD_SETUP 1 180 181#define OF_CPU "PowerPC,5200@0" 182#define OF_SOC "soc5200@f0000000" 183#define OF_TBCLK (bd->bi_busfreq / 4) 184 185#define CONFIG_BOARD_EARLY_INIT_R 186#define CONFIG_MISC_INIT_R 187 188/* 189 * Environment settings 190 */ 191#define CONFIG_ENV_IS_IN_FLASH 1 192#if defined(CONFIG_LOWBOOT) 193#define CONFIG_ENV_ADDR 0xFF060000 194#else /* CONFIG_LOWBOOT */ 195#define CONFIG_ENV_ADDR 0xFFF60000 196#endif /* CONFIG_LOWBOOT */ 197#define CONFIG_ENV_SIZE 0x10000 198#define CONFIG_ENV_SECT_SIZE 0x20000 199#define CONFIG_ENV_OVERWRITE 1 200 201/* 202 * Memory map 203 */ 204#define CONFIG_SYS_MBAR 0xF0000000 205#define CONFIG_SYS_SDRAM_BASE 0x00000000 206#if !defined(CONFIG_SYS_LOWBOOT) 207#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 208#else 209#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000 210#endif 211 212/* 213 * Use SRAM until RAM will be available 214 */ 215#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 216#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE 217 218#define CONFIG_SYS_GBL_DATA_SIZE 4096 219#define CONFIG_SYS_GBL_DATA_OFFSET \ 220 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 221#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 222 223#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 224#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 225#define CONFIG_SYS_RAMBOOT 1 226#endif 227 228#define CONFIG_SYS_MONITOR_LEN (256 << 10) 229#define CONFIG_SYS_MALLOC_LEN (4096 << 10) 230#define CONFIG_SYS_BOOTMAPSZ (8 << 20) 231 232/* 233 * Ethernet configuration 234 */ 235#define CONFIG_MPC5xxx_FEC 1 236#define CONFIG_MPC5xxx_FEC_MII100 237#define CONFIG_PHY_ADDR 0x00 238#define CONFIG_PHY_RESET_DELAY 1000 239 240#define CONFIG_NETCONSOLE /* include NetConsole support */ 241 242/* 243 * GPIO configuration 244 */ 245#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112 246 247/* 248 * Miscellaneous configurable options 249 */ 250#define CONFIG_SYS_LONGHELP 251#define CONFIG_AUTO_COMPLETE 1 252#define CONFIG_SYS_PROMPT "=> " 253#define CONFIG_SYS_HUSH_PARSER 254#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 255 256#define CONFIG_AUTOBOOT_KEYED 257#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay 258#define CONFIG_AUTOBOOT_DELAY_STR " " 259 260#define CONFIG_LOOPW 1 261#define CONFIG_MX_CYCLIC 1 262#define CONFIG_ZERO_BOOTDELAY_CHECK 263 264#define CONFIG_SYS_CBSIZE 1024 265#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 266#define CONFIG_SYS_MAXARGS 32 267#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 268 269#define CONFIG_SYS_ALT_MEMTEST 270#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000 271#define CONFIG_SYS_MEMTEST_START 0x00010000 272#define CONFIG_SYS_MEMTEST_END 0x019fffff 273 274#define CONFIG_SYS_LOAD_ADDR 0x00100000 275 276#define CONFIG_SYS_HZ 1000 277 278/* 279 * Various low-level settings 280 */ 281#define CONFIG_SYS_SDRAM_CS1 1 282#define CONFIG_SYS_XLB_PIPELINING 1 283 284#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 285#define CONFIG_SYS_HID0_FINAL HID0_ICE 286 287#if defined(CONFIG_SYS_LOWBOOT) 288#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 289#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 290#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 291#endif 292 293#define CONFIG_SYS_CS4_START 0x60000000 294#define CONFIG_SYS_CS4_SIZE 0x1000 295#define CONFIG_SYS_CS4_CFG 0x0008FC00 296 297#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 298#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 299#define CONFIG_SYS_CS0_CFG 0x0002DD00 300 301#define CONFIG_SYS_CS_BURST 0x00000000 302#define CONFIG_SYS_CS_DEADCYCLE 0x11111111 303 304#if !defined(CONFIG_SYS_LOWBOOT) 305#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 306#else 307#define CONFIG_SYS_RESET_ADDRESS 0xff000100 308#endif 309 310/* 311 * USB 312 */ 313#define CONFIG_USB_OHCI_NEW 314#define CONFIG_SYS_OHCI_BE_CONTROLLER 315#define CONFIG_USB_STORAGE 316 317#define CONFIG_USB_CLOCK 0x00013333 318#define CONFIG_USB_CONFIG 0x00002000 319 320#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 321#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB 322#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" 323#define CONFIG_SYS_USB_OHCI_CPU_INIT 324 325/* 326 * IDE/ATA 327 */ 328#define CONFIG_IDE_RESET 329#define CONFIG_IDE_PREINIT 330 331#define CONFIG_SYS_ATA_CS_ON_I2C2 332#define CONFIG_SYS_IDE_MAXBUS 1 333#define CONFIG_SYS_IDE_MAXDEVICE 1 334 335#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 336#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 337#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 338#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 339#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 340#define CONFIG_SYS_ATA_STRIDE 4 341 342#define CONFIG_ATAPI 1 343#define CONFIG_LBA48 1 344 345#endif /* __CONFIG_H */ 346