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31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34
35
36
37#define CONFIG_440EPX 1
38#define CONFIG_4xx 1
39#define CONFIG_SYS_CLK_FREQ 33333333
40
41#define CONFIG_BOARD_EARLY_INIT_F 1
42#define CONFIG_MISC_INIT_R 1
43
44
45
46
47#define MAN_DATA_EEPROM_ADDR 0x53
48#define MAN_INFO_FIELD 2
49#define MAN_INFO_LENGTH 9
50#define MAN_MAC_ADDR_FIELD 3
51#define MAN_MAC_ADDR_LENGTH 12
52
53
54
55
56
57#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
58#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
59
60#define CONFIG_SYS_SDRAM_BASE 0x00000000
61#define CONFIG_SYS_FLASH0_SIZE 0x01000000
62#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
63#define CONFIG_SYS_FLASH1_TOP 0xF8000000
64#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
65#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
66#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR
67#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
68#define CONFIG_SYS_OCM_BASE 0xe0010000
69#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
70#define CONFIG_SYS_PCI_BASE 0xe0000000
71#define CONFIG_SYS_PCI_MEMBASE 0x80000000
72
73
74#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000
75
76#define CONFIG_SYS_USB2D0_BASE 0xe0000100
77#define CONFIG_SYS_USB_DEVICE 0xe0000000
78#define CONFIG_SYS_USB_HOST 0xe0000400
79#define CONFIG_SYS_CPLD_BASE 0xc0000000
80
81
82
83
84
85#undef CONFIG_SYS_INIT_RAM_DCACHE
86#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
87#define CONFIG_SYS_INIT_RAM_END (4 << 10)
88#define CONFIG_SYS_GBL_DATA_SIZE 256
89#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
90#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
91
92
93
94
95#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200
96#define CONFIG_BAUDRATE 115200
97#define CONFIG_SERIAL_MULTI 1
98
99#undef CONFIG_UART1_CONSOLE
100
101#define CONFIG_SYS_BAUDRATE_TABLE \
102 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
103
104
105
106
107#define CONFIG_ENV_IS_IN_FLASH 1
108
109
110
111
112#define CONFIG_SYS_FLASH_CFI
113#define CONFIG_FLASH_CFI_DRIVER
114#define CONFIG_FLASH_CFI_LEGACY
115
116#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
117
118#define CONFIG_SYS_MAX_FLASH_BANKS 2
119#define CONFIG_SYS_MAX_FLASH_SECT 1024
120
121#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
122#define CONFIG_SYS_FLASH_WRITE_TOUT 500
123
124#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
125#define CONFIG_SYS_FLASH_PROTECTION 1
126
127#define CONFIG_SYS_FLASH_EMPTY_INFO
128#define CONFIG_SYS_FLASH_QUIET_TEST 1
129
130#define CONFIG_ENV_SECT_SIZE 0x20000
131#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
132#define CONFIG_ENV_SIZE 0x2000
133
134
135#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
136#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
137
138
139
140
141#define CONFIG_DDR_DATA_EYE
142#define CONFIG_SPD_EEPROM
143#define CONFIG_ZERO_SDRAM
144#define CONFIG_DDR_ECC
145#define SPD_EEPROM_ADDRESS {0x50}
146#define CONFIG_PROG_SDRAM_TLB
147#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
148
149
150
151
152
153#define CONFIG_HARD_I2C 1
154#undef CONFIG_SOFT_I2C
155#define CONFIG_SYS_I2C_SPEED 400000
156#define CONFIG_SYS_I2C_SLAVE 0x7F
157
158#define CONFIG_SYS_I2C_MULTI_EEPROMS
159#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
160#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
161#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
162#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
163
164
165#define CONFIG_RTC_M41T60 1
166#define CONFIG_SYS_I2C_RTC_ADDR 0x68
167
168
169#define CONFIG_DTT_LM73 1
170#define CONFIG_DTT_SENSORS {2}
171#define CONFIG_SYS_DTT_MAX_TEMP 70
172#define CONFIG_SYS_DTT_MIN_TEMP -30
173
174#define CONFIG_PREBOOT "echo;" \
175 "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
176 "echo"
177
178#undef CONFIG_BOOTARGS
179
180
181#define CONFIG_HOSTNAME korat
182
183
184#define CONFIG_EXTRA_ENV_SETTINGS \
185 "u_boot=korat/u-boot.bin\0" \
186 "load=tftp 200000 ${u_boot}\0" \
187 "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
188 "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
189 "F7F60000 F7FBFFFF\0" \
190 "upd=run load update\0" \
191 "bootfile=korat/uImage\0" \
192 "dtb=korat/korat.dtb\0" \
193 "kernel_addr=F4000000\0" \
194 "ramdisk_addr=F4400000\0" \
195 "dtb_addr=F41E0000\0" \
196 "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
197 "cp.b ${fileaddr} F4000000 ${filesize}\0" \
198 "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
199 "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
200 "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
201 "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
202 "${dtb}\0" \
203 "rd_size=73728\0" \
204 "ramargs=setenv bootargs root=/dev/ram rw " \
205 "ramdisk_size=${rd_size}\0" \
206 "usbdev=sda1\0" \
207 "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
208 "rootpath=/opt/eldk/ppc_4xxFP\0" \
209 "netdev=eth0\0" \
210 "nfsargs=setenv bootargs root=/dev/nfs rw " \
211 "nfsroot=${serverip}:${rootpath}\0" \
212 "pciclk=33\0" \
213 "addide=setenv bootargs ${bootargs} ide=reverse " \
214 "idebus=${pciclk}\0" \
215 "addip=setenv bootargs ${bootargs} " \
216 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
217 ":${hostname}:${netdev}:off panic=1\0" \
218 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
219 "flash_cf=run usbargs addide addip addtty; " \
220 "bootm ${kernel_addr} - ${dtb_addr}\0" \
221 "flash_nfs=run nfsargs addide addip addtty; " \
222 "bootm ${kernel_addr} - ${dtb_addr}\0" \
223 "flash_self=run ramargs addip addtty; " \
224 "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
225 ""
226
227#define CONFIG_BOOTCOMMAND "run flash_cf"
228
229#define CONFIG_BOOTDELAY 5
230
231#define CONFIG_LOADS_ECHO 1
232#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
233
234#define CONFIG_PPC4xx_EMAC
235#define CONFIG_IBM_EMAC4_V4 1
236#define CONFIG_MII 1
237#define CONFIG_PHY_ADDR 2
238#define CONFIG_PHY_DYNAMIC_ANEG 1
239
240#undef CONFIG_PHY_RESET
241#define CONFIG_PHY_GIGE 1
242
243#define CONFIG_HAS_ETH0
244#define CONFIG_SYS_RX_ETH_BUFFER 32
245
246#define CONFIG_NET_MULTI 1
247#define CONFIG_HAS_ETH1 1
248#define CONFIG_PHY1_ADDR 3
249
250
251#define CONFIG_USB_OHCI
252#define CONFIG_USB_STORAGE
253
254
255#define USB_2_0_DEVICE
256
257
258#define CONFIG_MAC_PARTITION
259#define CONFIG_DOS_PARTITION
260#define CONFIG_ISO_PARTITION
261
262
263
264
265#define CONFIG_BOOTP_BOOTFILESIZE
266#define CONFIG_BOOTP_BOOTPATH
267#define CONFIG_BOOTP_GATEWAY
268#define CONFIG_BOOTP_HOSTNAME
269#define CONFIG_BOOTP_SUBNETMASK
270
271
272
273
274#include <config_cmd_default.h>
275
276#define CONFIG_CMD_ASKENV
277#define CONFIG_CMD_DATE
278#define CONFIG_CMD_DHCP
279#define CONFIG_CMD_DTT
280#define CONFIG_CMD_DIAG
281#define CONFIG_CMD_EEPROM
282#define CONFIG_CMD_ELF
283#define CONFIG_CMD_FAT
284#define CONFIG_CMD_I2C
285#define CONFIG_I2C_CMD_TREE
286#define CONFIG_CMD_IRQ
287#define CONFIG_CMD_MII
288#define CONFIG_CMD_NET
289#define CONFIG_CMD_NFS
290#define CONFIG_CMD_PCI
291#define CONFIG_CMD_PING
292#define CONFIG_CMD_REGINFO
293#define CONFIG_CMD_SDRAM
294#define CONFIG_CMD_USB
295
296
297#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
298 CONFIG_SYS_POST_CPU | \
299 CONFIG_SYS_POST_ECC | \
300 CONFIG_SYS_POST_ETHER | \
301 CONFIG_SYS_POST_FPU | \
302 CONFIG_SYS_POST_I2C | \
303 CONFIG_SYS_POST_MEMORY | \
304 CONFIG_SYS_POST_RTC | \
305 CONFIG_SYS_POST_SPR | \
306 CONFIG_SYS_POST_UART)
307
308#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
309#define CONFIG_LOGBUFFER
310#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000
311
312#define CONFIG_SYS_CONSOLE_IS_IN_ENV
313
314#define CONFIG_SUPPORT_VFAT
315
316
317
318
319#define CONFIG_SYS_LONGHELP
320#define CONFIG_SYS_PROMPT "=> "
321#if defined(CONFIG_CMD_KGDB)
322#define CONFIG_SYS_CBSIZE 1024
323#else
324#define CONFIG_SYS_CBSIZE 256
325#endif
326#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
327
328#define CONFIG_SYS_MAXARGS 16
329#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
330
331#define CONFIG_SYS_MEMTEST_START 0x0400000
332#define CONFIG_SYS_MEMTEST_END 0x0C00000
333
334#define CONFIG_SYS_LOAD_ADDR 0x100000
335#define CONFIG_SYS_EXTBDINFO 1
336
337#define CONFIG_SYS_HZ 1000
338
339#define CONFIG_CMDLINE_EDITING 1
340#define CONFIG_LOOPW 1
341#define CONFIG_MX_CYCLIC 1
342#define CONFIG_ZERO_BOOTDELAY_CHECK
343#define CONFIG_VERSION_VARIABLE 1
344
345
346
347
348#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000
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352
353
354#define CONFIG_PCI
355#define CONFIG_PCI_PNP
356#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
357#define CONFIG_PCI_SCAN_SHOW
358#define CONFIG_SYS_PCI_TARGBASE 0x80000000
359
360
361#define CONFIG_SYS_PCI_TARGET_INIT
362#define CONFIG_SYS_PCI_MASTER_INIT
363
364#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8
365#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe
366
367
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371
372#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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377
378
379#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
380#define CONFIG_SYS_EBC_PB0AP 0x04017300
381#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
382#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
383#define CONFIG_SYS_EBC_PB0AP 0x04017300
384#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
385#else
386#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
387#endif
388
389
390#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
391#define CONFIG_SYS_EBC_PB1AP 0x04017300
392#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
393#else
394#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
395#endif
396
397
398#define CONFIG_SYS_EBC_PB2AP 0x04017300
399#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
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465
466#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
467#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
468#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
469#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
470#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
471#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
472#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
473#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
474#define CONFIG_SYS_GPIO_PHY0_EN 45
475#define CONFIG_SYS_GPIO_PHY1_EN 46
476#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
477
478
479
480
481#define CONFIG_SYS_4xx_GPIO_TABLE { \
482{ \
483 \
484{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
485{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
486{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
487{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, \
488{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, \
489{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, \
490{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
491{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
492{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
493{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
494{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
495{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
496{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
497{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, \
498{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
499{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
500{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
501{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
502{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
503{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
504{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
505{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
506{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
507{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
508{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
509{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
510{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
511{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
512{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
513{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
514{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
515{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
516}, \
517{ \
518 \
519{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
520{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, \
521{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
522{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
523{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
524{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
525{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
526{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
527{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
528{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
529{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
530{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
531{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
532{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
533{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, \
534{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
535{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
536{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
537{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
538{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
539{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
540{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
541{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
542{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
543{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
544{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
545{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
546{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
547{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
548{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
549{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
550{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
551} \
552}
553
554
555
556
557
558
559#define BOOTFLAG_COLD 0x01
560#define BOOTFLAG_WARM 0x02
561
562#if defined(CONFIG_CMD_KGDB)
563#define CONFIG_KGDB_BAUDRATE 230400
564#define CONFIG_KGDB_SER_INDEX 2
565#endif
566
567
568#define CONFIG_OF_LIBFDT 1
569#define CONFIG_OF_BOARD_SETUP 1
570
571#endif
572