LXR uboot/include/configs/m501sk.h

   1/*
   2 * Based on Modifications by Alan Lu / Artila and
   3 * Rick Bronson <rick@efn.org>
   4 *
   5 * Configuration settings for the Artila M-501 starter kit,
   6 * with V02 processor card.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#ifndef __CONFIG_H
  28#define __CONFIG_H
  29
  30/* ARM asynchronous clock */
  31/* from 18.432 MHz crystal (18432000 / 4 * 39) */
  32#define AT91C_MAIN_CLOCK        179712000
  33/* Perip clock (AT91C_MASTER_CLOCK / 3) */
  34#define AT91C_MASTER_CLOCK      59904000
  35#define AT91_SLOW_CLOCK 32768 /* slow clock */
  36
  37#define CONFIG_AT91RM9200DK     1 /* on an AT91RM9200DK Board    */
  38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  39#define CONFIG_CMDLINE_TAG      1 /* enable passing of ATAGs    */
  40#define CONFIG_SETUP_MEMORY_TAGS        1
  41#define CONFIG_INITRD_TAG               1
  42
  43#define CONFIG_MENUPROMPT               "."
  44/*
  45 * LowLevel Init
  46 */
  47#define CONFIG_SYS_USE_MAIN_OSCILLATOR          1
  48/* flash */
  49#define CONFIG_SYS_MC_PUIA_VAL  0x00000000
  50#define CONFIG_SYS_MC_PUP_VAL   0x00000000
  51#define CONFIG_SYS_MC_PUER_VAL  0x00000000
  52#define CONFIG_SYS_MC_ASR_VAL   0x00000000
  53#define CONFIG_SYS_MC_AASR_VAL  0x00000000
  54#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  55#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  56
  57/* clocks */
  58#define CONFIG_SYS_PLLAR_VAL    0x20263E04 /* 179.712000 MHz for PCK */
  59#define CONFIG_SYS_PLLBR_VAL    0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  60/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  61#define CONFIG_SYS_MCKR_VAL     0x00000202
  62
  63/* sdram */
  64#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  65#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  66#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  67#define CONFIG_SYS_EBI_CSA_VAL  0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  68#define CONFIG_SYS_SDRC_CR_VAL  0x2188c155 /* set up the CONFIG_SYS_SDRAM */
  69#define CONFIG_SYS_SDRAM        0x20000000 /* address of the CONFIG_SYS_SDRAM */
  70#define CONFIG_SYS_SDRAM1       0x20000080 /* address of the CONFIG_SYS_SDRAM */
  71#define CONFIG_SYS_SDRAM_VAL    0x00000000 /* value written to CONFIG_SYS_SDRAM */
  72#define CONFIG_SYS_SDRC_MR_VAL  0x00000002 /* Precharge All */
  73#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  74#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  75#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  76#define CONFIG_SYS_SDRC_TR_VAL  0x000002E0 /* Write refresh rate */
  77
  78/*
  79 * Size of malloc() pool
  80 */
  81#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128*1024)
  82#define CONFIG_SYS_GBL_DATA_SIZE        128     /* Bytes reserved for initial data */
  83
  84#define CONFIG_BAUDRATE                 115200
  85
  86/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
  87#define CONFIG_SYS_AT91C_BRGR_DIVISOR   33
  88
  89/*
  90 * Hardware drivers
  91 */
  92#define CONFIG_SYS_FLASH_CFI            1
  93#define CONFIG_FLASH_CFI_DRIVER 1
  94#define CONFIG_ENV_SECT_SIZE    0x20000
  95#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  96#define CONFIG_SYS_FLASH_PROTECTION     /*for Intel P30 Flash*/
  97#define CONFIG_HARD_I2C
  98#define CONFIG_SYS_I2C_SPEED            100
  99#define CONFIG_SYS_I2C_SLAVE            0
 100#define CONFIG_SYS_CONSOLE_INFO_QUIET
 101#undef CONFIG_ENV_IS_IN_EEPROM
 102#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 103#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 104#define CONFIG_SYS_EEPROM_AT24C16
 105#define CONFIG_SYS_I2C_RTC_ADDR         0x32
 106#undef CONFIG_RTC_DS1338
 107#define CONFIG_RTC_RS5C372A
 108#undef CONFIG_POST
 109#define CONFIG_M501SK
 110#define CONFIG_CMC_PU2
 111
 112/* define one of these to choose the DBGU, USART0  or USART1 as console */
 113#define CONFIG_AT91RM9200_USART
 114#define CONFIG_DBGU
 115#undef CONFIG_USART0
 116#undef CONFIG_USART1
 117
 118#undef CONFIG_HWFLOW            /* don't include RTS/CTS flow control support */
 119#undef CONFIG_MODEM_SUPPORT     /* disable modem initialization stuff */
 120
 121#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \
 122                        "initrd=0x20800000,8192000 ramdisk_size=15360 " \
 123                        "root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
 124                        "128k(loader)ro,128k(reserved)ro,1408k(linux)"  \
 125                        "ro,2560k(ramdisk)ro,-(userdisk)"
 126#define CONFIG_BOOTCOMMAND      "bootm 10040000 101a0000"
 127#define CONFIG_BOOTDELAY        1
 128#define CONFIG_BAUDRATE 115200
 129#define CONFIG_IPADDR           192.168.1.100
 130#define CONFIG_SERVERIP 192.168.1.1
 131#define CONFIG_GATEWAYIP        192.168.1.254
 132#define CONFIG_NETMASK          255.255.255.0
 133#define CONFIG_BOOTFILE uImage
 134#define CONFIG_ETHADDR          00:13:48:aa:bb:cc
 135#define CONFIG_ENV_OVERWRITE    1
 136#define BOARD_LATE_INIT
 137
 138#define CONFIG_EXTRA_ENV_SETTINGS \
 139                "unlock=yes\0"
 140
 141#define CONFIG_CMD_JFFS2
 142#undef CONFIG_CMD_EEPROM
 143#define CONFIG_CMD_NET
 144#define CONFIG_CMD_RUN
 145#define CONFIG_CMD_DHCP
 146#define CONFIG_CMD_MEMORY
 147#define CONFIG_CMD_PING
 148#define CONFIG_CMD_SDRAM
 149#define CONFIG_CMD_DIAG
 150#define CONFIG_CMD_I2C
 151#define CONFIG_CMD_DATE
 152#define CONFIG_CMD_POST
 153#define CONFIG_CMD_MISC
 154#define CONFIG_CMD_LOADS
 155#define CONFIG_CMD_IMI
 156#define CONFIG_CMD_NFS
 157#define CONFIG_CMD_FLASH
 158#define CONFIG_CMD_SAVEENV
 159
 160#define CONFIG_SYS_HUSH_PARSER
 161#define CONFIG_AUTO_COMPLETE
 162#define CONFIG_SYS_PROMPT_HUSH_PS2          ">>"
 163
 164#define CONFIG_SYS_MAX_NAND_DEVICE      0 /* Max number of NAND devices */
 165#define SECTORSIZE                           512
 166
 167#define ADDR_COLUMN             1
 168#define ADDR_PAGE               2
 169#define ADDR_COLUMN_PAGE        3
 170
 171#define CONFIG_NR_DRAM_BANKS    1
 172#define PHYS_SDRAM              0x20000000
 173#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
 174
 175#define CONFIG_SYS_MEMTEST_START        0x21000000 /* PHYS_SDRAM */
 176/* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
 177#define CONFIG_SYS_MEMTEST_END  0x00100000
 178
 179#define CONFIG_DRIVER_ETHER
 180#define CONFIG_NET_RETRY_COUNT  20
 181#define CONFIG_AT91C_USE_RMII
 182
 183#define PHYS_FLASH_1            0x10000000
 184#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
 185#define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 186#define CONFIG_SYS_MAX_FLASH_BANKS      1
 187#define CONFIG_SYS_MAX_FLASH_SECT       256
 188#define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 189#define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 190
 191#ifdef CONFIG_ENV_IS_IN_DATAFLASH
 192#define CONFIG_ENV_OFFSET               0x20000
 193#define CONFIG_ENV_ADDR         (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 194#define CONFIG_ENV_SIZE         0x2000
 195#else
 196#define CONFIG_ENV_IS_IN_FLASH
 197#define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + 0x00020000)
 198#define CONFIG_ENV_SIZE         2048
 199#endif
 200
 201#ifdef CONFIG_ENV_IS_IN_EEPROM
 202#define CONFIG_ENV_OFFSET               1024
 203#define CONFIG_ENV_SIZE         1024
 204#endif
 205
 206#define CONFIG_SYS_LOAD_ADDR            0x21000000 /* default load address */
 207
 208/* use for protect flash sectors */
 209#define CONFIG_SYS_BOOT_SIZE            0x6000 /* 24 KBytes */
 210#define CONFIG_SYS_U_BOOT_BASE  (PHYS_FLASH_1 + 0x10000)
 211#define CONFIG_SYS_U_BOOT_SIZE  0x10000 /* 64 KBytes */
 212
 213#define CONFIG_SYS_BAUDRATE_TABLE       { 115200 , 19200, 38400, 57600, 9600 }
 214
 215#define CONFIG_SYS_PROMPT               "U-Boot> " /* Monitor Command Prompt */
 216#define CONFIG_SYS_CBSIZE               512 /* Console I/O Buffer Size */
 217#define CONFIG_SYS_MAXARGS              16 /* max number of command args */
 218/* Print Buffer Size */
 219#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 220
 221#define CONFIG_SYS_HZ 1000
 222#define CONFIG_SYS_HZ_CLOCK             AT91C_MASTER_CLOCK/2
 223
 224#define CONFIG_STACKSIZE        (32*1024) /* regular stack */
 225
 226#ifdef CONFIG_USE_IRQ
 227#error CONFIG_USE_IRQ not supported
 228#endif
 229
 230#endif
 231