1/* 2 * (C) Copyright 2003-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2004-2005 6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27#ifndef __CONFIG_H 28#define __CONFIG_H 29 30/* 31 * High Level Configuration Options 32 * (easy to change) 33 */ 34 35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ 37#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ 38#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ 39#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ 40#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ 41 42#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 43 44#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 45#define BOOTFLAG_WARM 0x02 /* Software reboot */ 46 47#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 48 49/* 50 * Serial console configuration 51 */ 52#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ 53#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 54#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 55 56#ifdef CONFIG_STK52XX 57#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */ 58#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ 59#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ 60#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ 61#define CONFIG_BOARD_EARLY_INIT_R 62#endif /* CONFIG_STK52XX */ 63 64/* 65 * PCI Mapping: 66 * 0x40000000 - 0x4fffffff - PCI Memory 67 * 0x50000000 - 0x50ffffff - PCI IO Space 68 */ 69#ifdef CONFIG_STK52XX 70#define CONFIG_PCI 1 71#define CONFIG_PCI_PNP 1 72/* #define CONFIG_PCI_SCAN_SHOW 1 */ 73 74#define CONFIG_PCI_MEM_BUS 0x40000000 75#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 76#define CONFIG_PCI_MEM_SIZE 0x10000000 77 78#define CONFIG_PCI_IO_BUS 0x50000000 79#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 80#define CONFIG_PCI_IO_SIZE 0x01000000 81 82#define CONFIG_NET_MULTI 1 83#define CONFIG_EEPRO100 1 84#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 85#define CONFIG_NS8382X 1 86#endif /* CONFIG_STK52XX */ 87 88/* 89 * Video console 90 */ 91#if 1 92#define CONFIG_VIDEO 93#define CONFIG_VIDEO_SM501 94#define CONFIG_VIDEO_SM501_32BPP 95#define CONFIG_CFB_CONSOLE 96#define CONFIG_VIDEO_LOGO 97#define CONFIG_VGA_AS_SINGLE_DEVICE 98#define CONFIG_CONSOLE_EXTRA_INFO 99#define CONFIG_VIDEO_SW_CURSOR 100#define CONFIG_SPLASH_SCREEN 101#define CONFIG_SYS_CONSOLE_IS_IN_ENV 102#endif 103 104/* Partitions */ 105#define CONFIG_MAC_PARTITION 106#define CONFIG_DOS_PARTITION 107#define CONFIG_ISO_PARTITION 108 109/* USB */ 110#ifdef CONFIG_STK52XX 111#define CONFIG_USB_OHCI 112#define CONFIG_USB_STORAGE 113#endif 114 115/* POST support */ 116#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 117 CONFIG_SYS_POST_CPU | \ 118 CONFIG_SYS_POST_I2C) 119 120#ifdef CONFIG_POST 121/* preserve space for the post_word at end of on-chip SRAM */ 122#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 123#endif 124 125 126/* 127 * BOOTP options 128 */ 129#define CONFIG_BOOTP_BOOTFILESIZE 130#define CONFIG_BOOTP_BOOTPATH 131#define CONFIG_BOOTP_GATEWAY 132#define CONFIG_BOOTP_HOSTNAME 133 134 135/* 136 * Command line configuration. 137 */ 138#include <config_cmd_default.h> 139 140#define CONFIG_CMD_ASKENV 141#define CONFIG_CMD_DATE 142#define CONFIG_CMD_DHCP 143#define CONFIG_CMD_ECHO 144#define CONFIG_CMD_EEPROM 145#define CONFIG_CMD_I2C 146#define CONFIG_CMD_MII 147#define CONFIG_CMD_NFS 148#define CONFIG_CMD_PING 149#define CONFIG_CMD_REGINFO 150#define CONFIG_CMD_SNTP 151 152#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) 153 #define CONFIG_CMD_IDE 154 #define CONFIG_CMD_FAT 155 #define CONFIG_CMD_EXT2 156#endif 157 158#ifdef CONFIG_STK52XX 159 #define CONFIG_CMD_USB 160 #define CONFIG_CMD_FAT 161#endif 162 163#ifdef CONFIG_VIDEO 164 #define CONFIG_CMD_BMP 165#endif 166 167#ifdef CONFIG_PCI 168 #define CONFIG_CMD_PCI 169 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 170#endif 171 172#ifdef CONFIG_POST 173#define CONFIG_CMD_DIAG 174#endif 175 176 177#define CONFIG_TIMESTAMP /* display image timestamps */ 178 179#if (TEXT_BASE == 0xFC000000) /* Boot low */ 180# define CONFIG_SYS_LOWBOOT 1 181#endif 182 183/* 184 * Autobooting 185 */ 186#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 187 188#define CONFIG_PREBOOT "echo;" \ 189 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 190 "echo" 191 192#undef CONFIG_BOOTARGS 193 194#define CONFIG_EXTRA_ENV_SETTINGS \ 195 "netdev=eth0\0" \ 196 "rootpath=/opt/eldk/ppc_6xx\0" \ 197 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 198 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 199 "nfsroot=${serverip}:${rootpath}\0" \ 200 "addip=setenv bootargs ${bootargs} " \ 201 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 202 ":${hostname}:${netdev}:off panic=1\0" \ 203 "flash_self=run ramargs addip;" \ 204 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 205 "flash_nfs=run nfsargs addip;" \ 206 "bootm ${kernel_addr}\0" \ 207 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 208 "bootfile=/tftpboot/tqm5200/uImage\0" \ 209 "load=tftp 200000 ${u-boot}\0" \ 210 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ 211 "update=protect off FC000000 FC05FFFF;" \ 212 "erase FC000000 FC05FFFF;" \ 213 "cp.b 200000 FC000000 ${filesize};" \ 214 "protect on FC000000 FC05FFFF\0" \ 215 "" 216 217#define CONFIG_BOOTCOMMAND "run net_nfs" 218 219/* 220 * IPB Bus clocking configuration. 221 */ 222#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 223 224#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) 225/* 226 * PCI Bus clocking configuration 227 * 228 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if 229 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 230 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. 231 */ 232#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ 233#endif 234 235/* 236 * I2C configuration 237 */ 238#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 239#ifdef CONFIG_TQM5200_REV100 240#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ 241#else 242#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ 243#endif 244 245/* 246 * I2C clock frequency 247 * 248 * Please notice, that the resulting clock frequency could differ from the 249 * configured value. This is because the I2C clock is derived from system 250 * clock over a frequency divider with only a few divider values. U-boot 251 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated 252 * approximation allways lies below the configured value, never above. 253 */ 254#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 255#define CONFIG_SYS_I2C_SLAVE 0x7F 256 257/* 258 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work 259 * also). For other EEPROMs configuration should be verified. On Mini-FAP the 260 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the 261 * same configuration could be used. 262 */ 263#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 264#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 265#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ 266#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 267 268/* 269 * HW-Monitor configuration on Mini-FAP 270 */ 271#if defined (CONFIG_MINIFAP) 272#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C 273#endif 274 275/* List of I2C addresses to be verified by POST */ 276#if defined (CONFIG_MINIFAP) 277#undef I2C_ADDR_LIST 278#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \ 279 CONFIG_SYS_I2C_HWMON_ADDR, \ 280 CONFIG_SYS_I2C_SLAVE } 281#endif 282 283/* 284 * Flash configuration 285 */ 286#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */ 287 288/* use CFI flash driver if no module variant is spezified */ 289#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 290#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 291#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } 292#define CONFIG_SYS_FLASH_EMPTY_INFO 293#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ 294#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 295#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ 296 297#if !defined(CONFIG_SYS_LOWBOOT) 298#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) 299#else /* CONFIG_SYS_LOWBOOT */ 300#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) 301#endif /* CONFIG_SYS_LOWBOOT */ 302#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks 303 (= chip selects) */ 304#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 305#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 306 307 308/* 309 * Environment settings 310 */ 311#define CONFIG_ENV_IS_IN_FLASH 1 312#define CONFIG_ENV_SIZE 0x10000 313#define CONFIG_ENV_SECT_SIZE 0x20000 314#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 315#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 316 317/* 318 * Memory map 319 */ 320#define CONFIG_SYS_MBAR 0xF0000000 321#define CONFIG_SYS_SDRAM_BASE 0x00000000 322#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 323 324/* Use ON-Chip SRAM until RAM will be available */ 325#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 326#ifdef CONFIG_POST 327/* preserve space for the post_word at end of on-chip SRAM */ 328#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE 329#else 330#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE 331#endif 332 333 334#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 335#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 336#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 337 338#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 339#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 340# define CONFIG_SYS_RAMBOOT 1 341#endif 342 343#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ 344#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 345#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 346 347/* 348 * Ethernet configuration 349 */ 350#define CONFIG_MPC5xxx_FEC 1 351/* 352 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb 353 */ 354/* #define CONFIG_FEC_10MBIT 1 */ 355#define CONFIG_PHY_ADDR 0x00 356 357/* 358 * GPIO configuration 359 * 360 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): 361 * Bit 0 (mask: 0x80000000): 1 362 * use ALT CAN position: Bits 2-3 (mask: 0x30000000): 363 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. 364 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. 365 * Use for REV200 STK52XX boards. Do not use with REV100 modules 366 * (because, there I2C1 is used as I2C bus) 367 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 368 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) 369 * 000 -> All PSC2 pins are GIOPs 370 * 001 -> CAN1/2 on PSC2 pins 371 * Use for REV100 STK52xx boards 372 * use PSC6: 373 * on STK52xx: 374 * use as UART. Pins PSC6_0 to PSC6_3 are used. 375 * Bits 9:11 (mask: 0x00700000): 376 * 101 -> PSC6 : Extended POST test is not available 377 * on MINI-FAP and TQM5200_IB: 378 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): 379 * 000 -> PSC6 could not be used as UART, CODEC or IrDA 380 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST 381 * tests. 382 */ 383#if defined (CONFIG_MINIFAP) 384# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 385#elif defined (CONFIG_STK52XX) 386# if defined (CONFIG_STK52XX_REV100) 387# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 388# else /* STK52xx REV200 and above */ 389# if defined (CONFIG_TQM5200_REV100) 390# error TQM5200 REV100 not supported on STK52XX REV200 or above 391# else/* TQM5200 REV200 and above */ 392# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004 393# endif 394# endif 395#else /* TMQ5200 Inbetriebnahme-Board */ 396# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 397#endif 398 399/* 400 * RTC configuration 401 */ 402#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ 403 404/* 405 * Miscellaneous configurable options 406 */ 407#define CONFIG_SYS_LONGHELP /* undef to save memory */ 408#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 409#if defined(CONFIG_CMD_KGDB) 410#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 411#else 412#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 413#endif 414#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 415#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 416#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 417 418/* Enable an alternate, more extensive memory test */ 419#define CONFIG_SYS_ALT_MEMTEST 420 421#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 422#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 423 424#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 425 426#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 427 428#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 429#if defined(CONFIG_CMD_KGDB) 430# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 431#endif 432 433/* 434 * Enable loopw command. 435 */ 436#define CONFIG_LOOPW 437 438/* 439 * Various low-level settings 440 */ 441#if defined(CONFIG_MPC5200) 442#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 443#define CONFIG_SYS_HID0_FINAL HID0_ICE 444#else 445#define CONFIG_SYS_HID0_INIT 0 446#define CONFIG_SYS_HID0_FINAL 0 447#endif 448 449#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 450#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 451#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 452#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ 453#else 454#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ 455#endif 456#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 457#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 458 459#define CONFIG_LAST_STAGE_INIT 460 461/* 462 * SRAM - Do not map below 2 GB in address space, because this area is used 463 * for SDRAM autosizing. 464 */ 465#define CONFIG_SYS_CS2_START 0xE5000000 466#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ 467#define CONFIG_SYS_CS2_CFG 0x0004D930 468 469/* 470 * Grafic controller - Do not map below 2 GB in address space, because this 471 * area is used for SDRAM autosizing. 472 */ 473#define SM501_FB_BASE 0xE0000000 474#define CONFIG_SYS_CS1_START (SM501_FB_BASE) 475#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ 476#define CONFIG_SYS_CS1_CFG 0x8F48FF70 477#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 478 479#define CONFIG_SYS_CS_BURST 0x00000000 480#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ 481 482#define CONFIG_SYS_RESET_ADDRESS 0xff000000 483 484/*----------------------------------------------------------------------- 485 * USB stuff 486 *----------------------------------------------------------------------- 487 */ 488#define CONFIG_USB_CLOCK 0x0001BBBB 489#define CONFIG_USB_CONFIG 0x00001000 490 491/*----------------------------------------------------------------------- 492 * IDE/ATA stuff Supports IDE harddisk 493 *----------------------------------------------------------------------- 494 */ 495 496#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 497 498#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 499#undef CONFIG_IDE_LED /* LED for ide not supported */ 500 501#define CONFIG_IDE_RESET /* reset for ide supported */ 502#define CONFIG_IDE_PREINIT 503 504#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 505#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ 506 507#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 508 509#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 510 511/* Offset for data I/O */ 512#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 513 514/* Offset for normal register accesses */ 515#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 516 517/* Offset for alternate registers */ 518#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 519 520/* Interval between registers */ 521#define CONFIG_SYS_ATA_STRIDE 4 522 523#endif /* __CONFIG_H */ 524