LXR uboot/include/ppc4xx.h

   1/*----------------------------------------------------------------------------+
   2|
   3|       This source code has been made available to you by IBM on an AS-IS
   4|       basis.  Anyone receiving this source is licensed under IBM
   5|       copyrights to use it in any way he or she deems fit, including
   6|       copying it, modifying it, compiling it, and redistributing it either
   7|       with or without modifications.  No license under IBM patents or
   8|       patent applications is to be implied by the copyright license.
   9|
  10|       Any user of this software should understand that IBM cannot provide
  11|       technical support for this software and will not be responsible for
  12|       any consequences resulting from the use of this software.
  13|
  14|       Any person who transfers this source code or any derivative work
  15|       must include the IBM copyright notice, this paragraph, and the
  16|       preceding two paragraphs in the transferred software.
  17|
  18|       COPYRIGHT   I B M   CORPORATION 1999
  19|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20+----------------------------------------------------------------------------*/
  21
  22#ifndef __PPC4XX_H__
  23#define __PPC4XX_H__
  24
  25/*
  26 * Configure which SDRAM/DDR/DDR2 controller is equipped
  27 */
  28#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
  29        defined(CONFIG_AP1000) || defined(CONFIG_ML2)
  30#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM   /* IBM SDRAM controller */
  31#endif
  32
  33#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
  34    defined(CONFIG_440EP) || defined(CONFIG_440GR)
  35#define CONFIG_SDRAM_PPC4xx_IBM_DDR     /* IBM DDR controller */
  36#endif
  37
  38#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  39#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
  40#endif
  41
  42#if defined(CONFIG_405EX) || \
  43    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  44    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  45    defined(CONFIG_460SX)
  46#define CONFIG_SDRAM_PPC4xx_IBM_DDR2    /* IBM DDR(2) controller */
  47#endif
  48
  49#if defined(CONFIG_440EP) || defined(CONFIG_440GR) ||   \
  50    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  51    defined(CONFIG_405EZ) || defined(CONFIG_405EX) ||   \
  52    defined(CONFIG_460EX) || defined(CONFIG_460GT)
  53#define CONFIG_NAND_NDFC
  54#endif
  55
  56/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
  57#if defined(CONFIG_405EX) || \
  58    defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  59    defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  60    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  61    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
  62    defined(CONFIG_460SX)
  63
  64#define PLB_ARBITER_BASE                0x80
  65
  66#define plb0_revid                      (PLB_ARBITER_BASE + 0x00)
  67#define plb0_acr                        (PLB_ARBITER_BASE + 0x01)
  68#define plb0_acr_ppm_mask               0xF0000000
  69#define plb0_acr_ppm_fixed              0x00000000
  70#define plb0_acr_ppm_fair               0xD0000000
  71#define plb0_acr_hbu_mask               0x08000000
  72#define plb0_acr_hbu_disabled           0x00000000
  73#define plb0_acr_hbu_enabled            0x08000000
  74#define plb0_acr_rdp_mask               0x06000000
  75#define plb0_acr_rdp_disabled           0x00000000
  76#define plb0_acr_rdp_2deep              0x02000000
  77#define plb0_acr_rdp_3deep              0x04000000
  78#define plb0_acr_rdp_4deep              0x06000000
  79#define plb0_acr_wrp_mask               0x01000000
  80#define plb0_acr_wrp_disabled           0x00000000
  81#define plb0_acr_wrp_2deep              0x01000000
  82
  83#define plb0_besrl                      (PLB_ARBITER_BASE + 0x02)
  84#define plb0_besrh                      (PLB_ARBITER_BASE + 0x03)
  85#define plb0_bearl                      (PLB_ARBITER_BASE + 0x04)
  86#define plb0_bearh                      (PLB_ARBITER_BASE + 0x05)
  87#define plb0_ccr                        (PLB_ARBITER_BASE + 0x08)
  88
  89#define plb1_acr                        (PLB_ARBITER_BASE + 0x09)
  90#define plb1_acr_ppm_mask               0xF0000000
  91#define plb1_acr_ppm_fixed              0x00000000
  92#define plb1_acr_ppm_fair               0xD0000000
  93#define plb1_acr_hbu_mask               0x08000000
  94#define plb1_acr_hbu_disabled           0x00000000
  95#define plb1_acr_hbu_enabled            0x08000000
  96#define plb1_acr_rdp_mask               0x06000000
  97#define plb1_acr_rdp_disabled           0x00000000
  98#define plb1_acr_rdp_2deep              0x02000000
  99#define plb1_acr_rdp_3deep              0x04000000
 100#define plb1_acr_rdp_4deep              0x06000000
 101#define plb1_acr_wrp_mask               0x01000000
 102#define plb1_acr_wrp_disabled           0x00000000
 103#define plb1_acr_wrp_2deep              0x01000000
 104
 105#define plb1_besrl                      (PLB_ARBITER_BASE + 0x0A)
 106#define plb1_besrh                      (PLB_ARBITER_BASE + 0x0B)
 107#define plb1_bearl                      (PLB_ARBITER_BASE + 0x0C)
 108#define plb1_bearh                      (PLB_ARBITER_BASE + 0x0D)
 109
 110#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
 111
 112#if defined(CONFIG_440)
 113/*
 114 * Enable long long (%ll ...) printf format on 440 PPC's since most of
 115 * them support 36bit physical addressing
 116 */
 117#define CONFIG_SYS_64BIT_VSPRINTF
 118#define CONFIG_SYS_64BIT_STRTOUL
 119#include <ppc440.h>
 120#else
 121#include <ppc405.h>
 122#endif
 123
 124#include <asm/ppc4xx-sdram.h>
 125#include <asm/ppc4xx-ebc.h>
 126#if !defined(CONFIG_XILINX_440)
 127#include <asm/ppc4xx-uic.h>
 128#endif
 129
 130/*
 131 * Macro for generating register field mnemonics
 132 */
 133#define PPC_REG_BITS            32
 134#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
 135
 136/*
 137 * Elide casts when assembling register mnemonics
 138 */
 139#ifndef __ASSEMBLY__
 140#define static_cast(type, val)  (type)(val)
 141#else
 142#define static_cast(type, val)  (val)
 143#endif
 144
 145/*
 146 * Common stuff for 4xx (405 and 440)
 147 */
 148
 149#define EXC_OFF_SYS_RESET       0x0100  /* System reset                         */
 150#define _START_OFFSET           (EXC_OFF_SYS_RESET + 0x2000)
 151
 152#define RESET_VECTOR    0xfffffffc
 153#define CACHELINE_MASK  (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
 154                                                     line aligned data. */
 155
 156#define CPR0_DCR_BASE   0x0C
 157#define cprcfga         (CPR0_DCR_BASE+0x0)
 158#define cprcfgd         (CPR0_DCR_BASE+0x1)
 159
 160#define SDR_DCR_BASE    0x0E
 161#define sdrcfga         (SDR_DCR_BASE+0x0)
 162#define sdrcfgd         (SDR_DCR_BASE+0x1)
 163
 164#define SDRAM_DCR_BASE  0x10
 165#define memcfga         (SDRAM_DCR_BASE+0x0)
 166#define memcfgd         (SDRAM_DCR_BASE+0x1)
 167
 168#define EBC_DCR_BASE    0x12
 169#define ebccfga         (EBC_DCR_BASE+0x0)
 170#define ebccfgd         (EBC_DCR_BASE+0x1)
 171
 172/*
 173 * Macros for indirect DCR access
 174 */
 175#define mtcpr(reg, d)   do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
 176#define mfcpr(reg, d)   do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
 177
 178#define mtebc(reg, d)   do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
 179#define mfebc(reg, d)   do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
 180
 181#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
 182#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
 183
 184#define mtsdr(reg, d)   do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
 185#define mfsdr(reg, d)   do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
 186
 187#ifndef __ASSEMBLY__
 188
 189typedef struct
 190{
 191        unsigned long freqDDR;
 192        unsigned long freqEBC;
 193        unsigned long freqOPB;
 194        unsigned long freqPCI;
 195        unsigned long freqPLB;
 196        unsigned long freqTmrClk;
 197        unsigned long freqUART;
 198        unsigned long freqProcessor;
 199        unsigned long freqVCOHz;
 200        unsigned long freqVCOMhz;       /* in MHz                          */
 201        unsigned long pciClkSync;       /* PCI clock is synchronous        */
 202        unsigned long pciIntArbEn;      /* Internal PCI arbiter is enabled */
 203        unsigned long pllExtBusDiv;
 204        unsigned long pllFbkDiv;
 205        unsigned long pllFwdDiv;
 206        unsigned long pllFwdDivA;
 207        unsigned long pllFwdDivB;
 208        unsigned long pllOpbDiv;
 209        unsigned long pllPciDiv;
 210        unsigned long pllPlbDiv;
 211} PPC4xx_SYS_INFO;
 212
 213static inline u32 get_mcsr(void)
 214{
 215        u32 val;
 216
 217        asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
 218        return val;
 219}
 220
 221static inline void set_mcsr(u32 val)
 222{
 223        asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 224}
 225
 226#endif  /* __ASSEMBLY__ */
 227
 228/* for multi-cpu support */
 229#define NA_OR_UNKNOWN_CPU       -1
 230
 231#endif  /* __PPC4XX_H__ */
 232