1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#include <common.h>
24
25#if defined(CONFIG_CMD_NAND)
26
27#include <nand.h>
28#include <asm/arch/pxa-regs.h>
29
30#ifdef CONFIG_SYS_DFC_DEBUG1
31# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
32#else
33# define DFC_DEBUG1(fmt, args...)
34#endif
35
36#ifdef CONFIG_SYS_DFC_DEBUG2
37# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
38#else
39# define DFC_DEBUG2(fmt, args...)
40#endif
41
42#ifdef CONFIG_SYS_DFC_DEBUG3
43# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
44#else
45# define DFC_DEBUG3(fmt, args...)
46#endif
47
48
49static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
50
51static struct nand_bbt_descr delta_bbt_descr = {
52 .options = 0,
53 .offs = 0,
54 .len = 2,
55 .pattern = scan_ff_pattern
56};
57
58static struct nand_ecclayout delta_oob = {
59 .eccbytes = 6,
60 .eccpos = {2, 3, 4, 5, 6, 7},
61 .oobfree = { {8, 2}, {12, 4} }
62};
63
64
65
66
67static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
68{
69 return;
70}
71
72#if 0
73
74static int dfc_device_ready(struct mtd_info *mtdinfo)
75{
76 if(NDSR & NDSR_RDY)
77 return 1;
78 else
79 return 0;
80 return 0;
81}
82#endif
83
84
85
86
87static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
88{
89 unsigned long bytes_multi = len & 0xfffffffc;
90 unsigned long rest = len & 0x3;
91 unsigned long *long_buf;
92 int i;
93
94 DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
95 if(bytes_multi) {
96 for(i=0; i<bytes_multi; i+=4) {
97 long_buf = (unsigned long*) &buf[i];
98 NDDB = *long_buf;
99 }
100 }
101 if(rest) {
102 printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
103 }
104 return;
105}
106
107
108static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
109{
110 int i=0, j;
111
112
113
114 unsigned long bytes_multi = len & 0xfffffffc;
115 unsigned long rest = len & 0x3;
116 unsigned long *long_buf;
117
118 DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
119
120 if(bytes_multi) {
121 for(i=0; i<bytes_multi; i+=4) {
122 long_buf = (unsigned long*) &buf[i];
123 *long_buf = NDDB;
124 }
125 }
126
127
128 if(rest) {
129 unsigned long rest_data = NDDB;
130 for(j=0;j<rest; j++)
131 buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
132 }
133
134 return;
135}
136
137
138
139
140static u16 dfc_read_word(struct mtd_info *mtd)
141{
142 printf("dfc_read_word: UNIMPLEMENTED.\n");
143 return 0;
144}
145
146
147static unsigned long read_buf = 0;
148static int bytes_read = -1;
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163static u_char dfc_read_byte(struct mtd_info *mtd)
164{
165 unsigned char byte;
166 unsigned long dummy;
167
168 if(bytes_read < 0) {
169 read_buf = NDDB;
170 dummy = NDDB;
171 bytes_read = 0;
172 }
173 byte = (unsigned char) (read_buf>>(8 * bytes_read++));
174 if(bytes_read >= 4)
175 bytes_read = -1;
176
177 DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
178 return byte;
179}
180
181
182static unsigned long get_delta(unsigned long start)
183{
184 unsigned long cur = OSCR;
185
186 if(cur < start)
187 return (cur + (start^0xffffffff));
188 else
189 return (cur - start);
190}
191
192
193static void wait_us(unsigned long us)
194{
195 unsigned long start = OSCR;
196 us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
197
198 while (get_delta(start) < us) {
199
200 }
201}
202
203static void dfc_clear_nddb(void)
204{
205 NDCR &= ~NDCR_ND_RUN;
206 wait_us(CONFIG_SYS_NAND_OTHER_TO);
207}
208
209
210static unsigned long dfc_wait_event(unsigned long event)
211{
212 unsigned long ndsr, timeout, start = OSCR;
213
214 if(!event)
215 return 0xff000000;
216 else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
217 timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
218 * OSCR_CLK_FREQ, 1000);
219 else
220 timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
221 * OSCR_CLK_FREQ, 1000);
222
223 while(1) {
224 ndsr = NDSR;
225 if(ndsr & event) {
226 NDSR |= event;
227 break;
228 }
229 if(get_delta(start) > timeout) {
230 DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
231 return 0xff000000;
232 }
233
234 }
235 return ndsr;
236}
237
238
239static void dfc_new_cmd(void)
240{
241 int retry = 0;
242 unsigned long status;
243
244 while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
245
246 NDSR = 0xFFF;
247
248
249 if(!(NDCR & NDCR_ND_RUN))
250 NDCR |= NDCR_ND_RUN;
251
252 status = dfc_wait_event(NDSR_WRCMDREQ);
253
254 if(status & NDSR_WRCMDREQ)
255 return;
256
257 DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
258 dfc_clear_nddb();
259 }
260 DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
261}
262
263
264
265static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
266{
267 unsigned long ndsr=0, event=0;
268 int state = this->state;
269
270 if(state == FL_WRITING) {
271 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
272 } else if(state == FL_ERASING) {
273 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
274 }
275
276 ndsr = dfc_wait_event(event);
277
278 if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
279 return(0x1);
280 return 0;
281}
282
283
284static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
285 int column, int page_addr)
286{
287
288 unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
289
290
291 bytes_read = -1;
292 read_buf = 0;
293
294 switch (command) {
295 case NAND_CMD_READ0:
296 DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
297 dfc_new_cmd();
298 ndcb0 = (NAND_CMD_READ0 | (4<<16));
299 column >>= 1;
300 ndcb1 = (((column>>1) & 0xff) |
301 ((page_addr<<8) & 0xff00) |
302 ((page_addr<<8) & 0xff0000) |
303 ((page_addr<<8) & 0xff000000));
304 event = NDSR_RDDREQ;
305 goto write_cmd;
306 case NAND_CMD_READ1:
307 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
308 goto end;
309 case NAND_CMD_READOOB:
310 DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
311 goto end;
312 case NAND_CMD_READID:
313 dfc_new_cmd();
314 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
315 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16));
316 event = NDSR_RDDREQ;
317 goto write_cmd;
318 case NAND_CMD_PAGEPROG:
319
320 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
321 goto end;
322 case NAND_CMD_ERASE1:
323 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
324 dfc_new_cmd();
325 ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
326 ndcb1 = (page_addr & 0x00ffffff);
327 goto write_cmd;
328 case NAND_CMD_ERASE2:
329 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
330 goto end;
331 case NAND_CMD_SEQIN:
332
333 dfc_new_cmd();
334 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
335 ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
336 column >>= 1;
337 ndcb1 = (((column>>1) & 0xff) |
338 ((page_addr<<8) & 0xff00) |
339 ((page_addr<<8) & 0xff0000) |
340 ((page_addr<<8) & 0xff000000));
341 event = NDSR_WRDREQ;
342 goto write_cmd;
343 case NAND_CMD_STATUS:
344 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
345 dfc_new_cmd();
346 ndcb0 = NAND_CMD_STATUS | (4<<21);
347 event = NDSR_RDDREQ;
348 goto write_cmd;
349 case NAND_CMD_RESET:
350 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
351 ndcb0 = NAND_CMD_RESET | (5<<21);
352 event = NDSR_CS0_CMDD;
353 goto write_cmd;
354 default:
355 printk("dfc_cmdfunc: error, unsupported command.\n");
356 goto end;
357 }
358
359 write_cmd:
360 NDCB0 = ndcb0;
361 NDCB0 = ndcb1;
362 NDCB0 = ndcb2;
363
364
365 dfc_wait_event(event);
366 end:
367 return;
368}
369
370static void dfc_gpio_init(void)
371{
372 DFC_DEBUG2("Setting up DFC GPIO's.\n");
373
374
375 GPIO4 = 0x1;
376
377 DF_ALE_WE1 = 0x00000001;
378 DF_ALE_WE2 = 0x00000001;
379 DF_nCS0 = 0x00000001;
380 DF_nCS1 = 0x00000001;
381 DF_nWE = 0x00000001;
382 DF_nRE = 0x00000001;
383 DF_IO0 = 0x00000001;
384 DF_IO8 = 0x00000001;
385 DF_IO1 = 0x00000001;
386 DF_IO9 = 0x00000001;
387 DF_IO2 = 0x00000001;
388 DF_IO10 = 0x00000001;
389 DF_IO3 = 0x00000001;
390 DF_IO11 = 0x00000001;
391 DF_IO4 = 0x00000001;
392 DF_IO12 = 0x00000001;
393 DF_IO5 = 0x00000001;
394 DF_IO13 = 0x00000001;
395 DF_IO6 = 0x00000001;
396 DF_IO14 = 0x00000001;
397 DF_IO7 = 0x00000001;
398 DF_IO15 = 0x00000001;
399
400 DF_nWE = 0x1901;
401 DF_nRE = 0x1901;
402 DF_CLE_NOE = 0x1900;
403 DF_ALE_WE1 = 0x1901;
404 DF_INT_RnB = 0x1900;
405}
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425int board_nand_init(struct nand_chip *nand)
426{
427 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
428
429
430 dfc_gpio_init();
431
432
433 CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
434
435#undef CONFIG_SYS_TIMING_TIGHT
436#ifndef CONFIG_SYS_TIMING_TIGHT
437 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
438 DFC_MAX_tCH);
439 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
440 DFC_MAX_tCS);
441 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
442 DFC_MAX_tWH);
443 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
444 DFC_MAX_tWP);
445 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
446 DFC_MAX_tRH);
447 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
448 DFC_MAX_tRP);
449 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
450 DFC_MAX_tR);
451 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
452 DFC_MAX_tWHR);
453 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
454 DFC_MAX_tAR);
455#else
456
457 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
458 DFC_MAX_tCH);
459 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
460 DFC_MAX_tCS);
461 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
462 DFC_MAX_tWH);
463 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
464 DFC_MAX_tWP);
465 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
466 DFC_MAX_tRH);
467 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
468 DFC_MAX_tRP);
469 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
470 DFC_MAX_tR);
471 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
472 DFC_MAX_tWHR);
473 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
474 DFC_MAX_tAR);
475#endif
476
477
478 DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
479
480
481 if(tRP & (1 << 4)) {
482 tRP_high = 1;
483 tRP &= ~(1 << 4);
484 } else {
485 tRP_high = 0;
486 }
487
488 NDTR0CS0 = (tCH << 19) |
489 (tCS << 16) |
490 (tWH << 11) |
491 (tWP << 8) |
492 (tRP_high << 6) |
493 (tRH << 3) |
494 (tRP << 0);
495
496 NDTR1CS0 = (tR << 16) |
497 (tWHR << 4) |
498 (tAR << 0);
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515 NDCR = (NDCR_SPARE_EN |
516 NDCR_DWIDTH_C |
517 NDCR_DWIDTH_M |
518 (2 << 16) |
519 NDCR_ND_ARB_EN |
520 NDCR_RDYM |
521 NDCR_CS0_PAGEDM |
522 NDCR_CS1_PAGEDM |
523 NDCR_CS0_CMDDM |
524 NDCR_CS1_CMDDM |
525 NDCR_CS0_BBDM |
526 NDCR_CS1_BBDM |
527 NDCR_DBERRM |
528 NDCR_SBERRM |
529 NDCR_WRDREQM |
530 NDCR_RDDREQM |
531 NDCR_WRCMDREQM);
532
533
534
535
536
537
538 nand->cmd_ctrl = dfc_hwcontrol;
539
540 nand->ecc.mode = NAND_ECC_SOFT;
541 nand->ecc.layout = &delta_oob;
542 nand->options = NAND_BUSWIDTH_16;
543 nand->waitfunc = dfc_wait;
544 nand->read_byte = dfc_read_byte;
545 nand->read_word = dfc_read_word;
546 nand->read_buf = dfc_read_buf;
547 nand->write_buf = dfc_write_buf;
548
549 nand->cmdfunc = dfc_cmdfunc;
550 nand->badblock_pattern = &delta_bbt_descr;
551 return 0;
552}
553
554#endif
555