LXR uboot/board/mbx8xx/mbx8xx.c

   1/*
   2 * (C) Copyright 2000
   3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4 * Marius Groeger <mgroeger@sysgo.de>
   5 *
   6 * Board specific routines for the MBX
   7 *
   8 * - initialisation
   9 * - interface to VPD data (mac address, clock speeds)
  10 * - memory controller
  11 * - serial io initialisation
  12 * - ethernet io initialisation
  13 *
  14 * -----------------------------------------------------------------
  15 * See file CREDITS for list of people who contributed to this
  16 * project.
  17 *
  18 * This program is free software; you can redistribute it and/or
  19 * modify it under the terms of the GNU General Public License as
  20 * published by the Free Software Foundation; either version 2 of
  21 * the License, or (at your option) any later version.
  22 *
  23 * This program is distributed in the hope that it will be useful,
  24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26 * GNU General Public License for more details.
  27 *
  28 * You should have received a copy of the GNU General Public License
  29 * along with this program; if not, write to the Free Software
  30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31 * MA 02111-1307 USA
  32 */
  33
  34#include <common.h>
  35#include <commproc.h>
  36#include <mpc8xx.h>
  37#include <net.h>
  38#include "dimm.h"
  39#include "vpd.h"
  40#include "csr.h"
  41
  42/* ------------------------------------------------------------------------- */
  43
  44static const uint sdram_table_40[] = {
  45        /* DRAM - single read. (offset 0 in upm RAM)
  46         */
  47        0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
  48        0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
  49
  50        /* DRAM - burst read. (offset 8 in upm RAM)
  51         */
  52        0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
  53        0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
  54        0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
  55        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
  56
  57        /* DRAM - single write. (offset 18 in upm RAM)
  58         */
  59        0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804,
  60        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
  61
  62        /* DRAM - burst write. (offset 20 in upm RAM)
  63         */
  64        0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
  65        0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
  66        0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
  67        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
  68
  69        /* refresh  (offset 30 in upm RAM)
  70         */
  71        0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
  72        0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
  73        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
  74
  75        /* exception. (offset 3c in upm RAM)
  76         */
  77        0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
  78};
  79
  80static const uint sdram_table_50[] = {
  81        /* DRAM - single read. (offset 0 in upm RAM)
  82         */
  83        0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
  84        0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
  85
  86        /* DRAM - burst read. (offset 8 in upm RAM)
  87         */
  88        0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04,
  89  /*    0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */
  90        0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08,
  91        0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04,
  92  /*    0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */
  93        0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005,
  94
  95        /* DRAM - single write. (offset 18 in upm RAM)
  96         */
  97        0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
  98        0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
  99
 100        /* DRAM - burst write. (offset 20 in upm RAM)
 101         */
 102        0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
 103        0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
 104        0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
 105        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
 106
 107        /* refresh  (offset 30 in upm RAM)
 108         */
 109        0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
 110        0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
 111        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
 112
 113        /* exception. (offset 3c in upm RAM)
 114         */
 115        0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
 116};
 117
 118/* ------------------------------------------------------------------------- */
 119
 120static unsigned int get_reffreq(void);
 121static unsigned int board_get_cpufreq(void);
 122
 123void mbx_init (void)
 124{
 125        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 126        volatile memctl8xx_t *memctl = &immr->im_memctl;
 127        ulong speed, refclock, plprcr, sccr;
 128        ulong br0_32 = memctl->memc_br0 & 0x400;
 129
 130        /* real-time clock status and control register */
 131        immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
 132        immr->im_sit.sit_rtcsc = 0x00C3;
 133
 134        /* SIEL and SIMASK Registers (see MBX PRG 2-3) */
 135        immr->im_siu_conf.sc_simask = 0x00000000;
 136        immr->im_siu_conf.sc_siel = 0xAAAA0000;
 137        immr->im_siu_conf.sc_tesr = 0xFFFFFFFF;
 138
 139        /*
 140         * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus:
 141         * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h)
 142         * 2. RAM  Specs (see dimm.h)
 143         * 2. DIMM Specs (see dimm.h)
 144         */
 145        vpd_init ();
 146
 147        /* system clock and reset control register */
 148        immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
 149        sccr = immr->im_clkrst.car_sccr;
 150        sccr &= SCCR_MASK;
 151        sccr |= CONFIG_SYS_SCCR;
 152        immr->im_clkrst.car_sccr = sccr;
 153
 154        speed = board_get_cpufreq ();
 155        refclock = get_reffreq ();
 156
 157#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
 158        plprcr = CONFIG_SYS_PLPRCR;
 159#else
 160        plprcr = immr->im_clkrst.car_plprcr;
 161        plprcr &= PLPRCR_MF_MSK;        /* isolate MF field */
 162        plprcr |= CONFIG_SYS_PLPRCR;            /* reset control bits   */
 163#endif
 164
 165#ifdef CONFIG_SYS_USE_OSCCLK                    /* See doc/README.MBX ! */
 166        plprcr |= ((speed + refclock / 2) / refclock - 1) << 20;
 167#endif
 168
 169        immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
 170        immr->im_clkrst.car_plprcr = plprcr;
 171
 172        /*
 173         * preliminary setup of memory controller:
 174         * - map Flash, otherwise configuration/status
 175         *    registers won't be accessible when read
 176         *    by board_init_f.
 177         * - map NVRAM and configuation/status registers.
 178         * - map pci registers.
 179         * - DON'T map ram yet, this is done in initdram().
 180         */
 181        switch (speed / 1000000) {
 182        case 40:
 183                memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
 184                memctl->memc_or0 = 0xFF800930;
 185                memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920;
 186                memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
 187                break;
 188        case 50:
 189                memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
 190                memctl->memc_or0 = 0xFF800940;
 191                memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930;
 192                memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
 193                break;
 194        default:
 195                hang ();
 196                break;
 197        }
 198#ifdef CONFIG_USE_PCI
 199        memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR;
 200        memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001;
 201        memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR;
 202        memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001;
 203#endif
 204        /*
 205         * FIXME: I do not understand why I have to call this to
 206         * initialise the control register here before booting from
 207         * the PCMCIA card but if I do not the Linux kernel falls
 208         * over in a big heap. If you can answer this question I
 209         * would like to know about it.
 210         */
 211        board_ether_init();
 212}
 213
 214void board_serial_init (void)
 215{
 216        MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS);
 217}
 218
 219void board_ether_init (void)
 220{
 221        MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN);
 222        MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS;
 223}
 224
 225static unsigned int board_get_cpufreq (void)
 226{
 227#ifndef CONFIG_8xx_GCLK_FREQ
 228        vpd_packet_t *packet;
 229
 230        packet = vpd_find_packet (VPD_PID_ICS);
 231        return *((ulong *) packet->data);
 232#else
 233        return((unsigned int)CONFIG_8xx_GCLK_FREQ );
 234#endif /* CONFIG_8xx_GCLK_FREQ */
 235}
 236
 237static unsigned int get_reffreq (void)
 238{
 239        vpd_packet_t *packet;
 240
 241        packet = vpd_find_packet (VPD_PID_RCS);
 242        return *((ulong *) packet->data);
 243}
 244
 245static void board_get_enetaddr(uchar *addr)
 246{
 247        int i;
 248        vpd_packet_t *packet;
 249
 250        packet = vpd_find_packet (VPD_PID_EA);
 251        for (i = 0; i < 6; i++)
 252                addr[i] = packet->data[i];
 253}
 254
 255int misc_init_r(void)
 256{
 257        uchar enetaddr[6];
 258
 259        if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 260                board_get_enetaddr(enetaddr);
 261                eth_setenv_enetaddr("ethaddr", enetaddr);
 262        }
 263
 264        return 0;
 265}
 266
 267/*
 268 * Check Board Identity:
 269 */
 270
 271int checkboard (void)
 272{
 273        vpd_packet_t *packet;
 274        int i;
 275        const char *const fmt =
 276                "\n      *** Warning: Low Battery Status - %s Battery ***";
 277
 278        puts ("Board: ");
 279
 280        packet = vpd_find_packet (VPD_PID_PID);
 281        for (i = 0; i < packet->size; i++) {
 282                serial_putc (packet->data[i]);
 283        }
 284        packet = vpd_find_packet (VPD_PID_MT);
 285        for (i = 0; i < packet->size; i++) {
 286                serial_putc (packet->data[i]);
 287        }
 288        serial_putc ('(');
 289        packet = vpd_find_packet (VPD_PID_FAN);
 290        for (i = 0; i < packet->size; i++) {
 291                serial_putc (packet->data[i]);
 292        }
 293        serial_putc (')');
 294
 295        if (!(MBX_CSR2 & SR2_BATGD))
 296                printf (fmt, "On-Board");
 297        if (!(MBX_CSR2 & SR2_NVBATGD))
 298                printf (fmt, "NVRAM");
 299
 300        serial_putc ('\n');
 301
 302        return (0);
 303}
 304
 305/* ------------------------------------------------------------------------- */
 306
 307static ulong get_ramsize (dimm_t * dimm)
 308{
 309        ulong size = 0;
 310
 311        if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3
 312                || dimm->fmt == 4) {
 313                size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks *
 314                        ((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8);
 315        }
 316
 317        return size;
 318}
 319
 320phys_size_t initdram (int board_type)
 321{
 322        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 323        volatile memctl8xx_t *memctl = &immap->im_memctl;
 324        unsigned long ram_sz = 0;
 325        unsigned long dimm_sz = 0;
 326        dimm_t vpd_dimm, vpd_dram;
 327        unsigned int speed = board_get_cpufreq () / 1000000;
 328
 329        if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) {
 330                dimm_sz = get_ramsize (&vpd_dimm);
 331        }
 332        if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) {
 333                ram_sz = get_ramsize (&vpd_dram);
 334        }
 335
 336        /*
 337         * Only initialize memory controller when running from FLASH.
 338         * When running from RAM, don't touch it.
 339         */
 340        if ((ulong) initdram & 0xff000000) {
 341                ulong dimm_bank;
 342                ulong br0_32 = memctl->memc_br0 & 0x400;
 343
 344                switch (speed) {
 345                case 40:
 346                        upmconfig (UPMA, (uint *) sdram_table_40,
 347                                           sizeof (sdram_table_40) / sizeof (uint));
 348                        memctl->memc_mptpr = 0x0200;
 349                        memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000;
 350                        memctl->memc_or7 = 0xff800930;
 351                        memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
 352                        break;
 353                case 50:
 354                        upmconfig (UPMA, (uint *) sdram_table_50,
 355                                           sizeof (sdram_table_50) / sizeof (uint));
 356                        memctl->memc_mptpr = 0x0200;
 357                        memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100;
 358                        memctl->memc_or7 = 0xff800940;
 359                        memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
 360                        break;
 361                default:
 362                        hang ();
 363                        break;
 364                }
 365
 366                /* now map ram and dimm, largest one first */
 367                dimm_bank = dimm_sz / 2;
 368                if (!dimm_sz) {
 369                        memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
 370                        memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
 371                        memctl->memc_br2 = 0;
 372                        memctl->memc_br3 = 0;
 373                } else if (ram_sz > dimm_bank) {
 374                        memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
 375                        memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
 376                        memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
 377                        memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81;
 378                        memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
 379                        memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \
 380                                                                     | 0x81;
 381                } else {
 382                        memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
 383                        memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81;
 384                        memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
 385                        memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81;
 386                        memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
 387                        memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81;
 388                }
 389        }
 390
 391        return ram_sz + dimm_sz;
 392}
 393