LXR uboot/board/omap1510inn/lowlevel

   1/*
   2 * Board specific setup info
   3 *
   4 * (C) Copyright 2003
   5 * Texas Instruments, <www.ti.com>
   6 *
   7 * -- Some bits of code used from rrload's head_OMAP1510.s --
   8 * Copyright (C) 2002 RidgeRun, Inc.
   9 *
  10 * See file CREDITS for list of people who contributed to this
  11 * project.
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License as
  15 * published by the Free Software Foundation; either version 2 of
  16 * the License, or (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 * MA 02111-1307 USA
  27 */
  28
  29#include <config.h>
  30#include <version.h>
  31
  32#if defined(CONFIG_OMAP1510)
  33#include <./configs/omap1510.h>
  34#endif
  35
  36#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
  37
  38
  39_TEXT_BASE:
  40        .word   TEXT_BASE        /* sdram load addr from config.mk */
  41
  42.globl lowlevel_init
  43lowlevel_init:
  44
  45        /*
  46         * Configure 1510 pins functions to match our board.
  47         */
  48        ldr     r0, REG_PULL_DWN_CTRL_0
  49        ldr     r1, VAL_PULL_DWN_CTRL_0
  50        str     r1, [r0]
  51        ldr     r0, REG_PULL_DWN_CTRL_1
  52        ldr     r1, VAL_PULL_DWN_CTRL_1
  53        str     r1, [r0]
  54        ldr     r0, REG_PULL_DWN_CTRL_2
  55        ldr     r1, VAL_PULL_DWN_CTRL_2
  56        str     r1, [r0]
  57        ldr     r0, REG_PULL_DWN_CTRL_3
  58        ldr     r1, VAL_PULL_DWN_CTRL_3
  59        str     r1, [r0]
  60        ldr     r0, REG_FUNC_MUX_CTRL_4
  61        ldr     r1, VAL_FUNC_MUX_CTRL_4
  62        str     r1, [r0]
  63        ldr     r0, REG_FUNC_MUX_CTRL_5
  64        ldr     r1, VAL_FUNC_MUX_CTRL_5
  65        str     r1, [r0]
  66        ldr     r0, REG_FUNC_MUX_CTRL_6
  67        ldr     r1, VAL_FUNC_MUX_CTRL_6
  68        str     r1, [r0]
  69        ldr     r0, REG_FUNC_MUX_CTRL_7
  70        ldr     r1, VAL_FUNC_MUX_CTRL_7
  71        str     r1, [r0]
  72        ldr     r0, REG_FUNC_MUX_CTRL_8
  73        ldr     r1, VAL_FUNC_MUX_CTRL_8
  74        str     r1, [r0]
  75        ldr     r0, REG_FUNC_MUX_CTRL_9
  76        ldr     r1, VAL_FUNC_MUX_CTRL_9
  77        str     r1, [r0]
  78        ldr     r0, REG_FUNC_MUX_CTRL_A
  79        ldr     r1, VAL_FUNC_MUX_CTRL_A
  80        str     r1, [r0]
  81        ldr     r0, REG_FUNC_MUX_CTRL_B
  82        ldr     r1, VAL_FUNC_MUX_CTRL_B
  83        str     r1, [r0]
  84        ldr     r0, REG_FUNC_MUX_CTRL_C
  85        ldr     r1, VAL_FUNC_MUX_CTRL_C
  86        str     r1, [r0]
  87        ldr     r0, REG_FUNC_MUX_CTRL_D
  88        ldr     r1, VAL_FUNC_MUX_CTRL_D
  89        str     r1, [r0]
  90        ldr     r0, REG_VOLTAGE_CTRL_0
  91        ldr     r1, VAL_VOLTAGE_CTRL_0
  92        str     r1, [r0]
  93        ldr     r0, REG_TEST_DBG_CTRL_0
  94        ldr     r1, VAL_TEST_DBG_CTRL_0
  95        str     r1, [r0]
  96        ldr     r0, REG_MOD_CONF_CTRL_0
  97        ldr     r1, VAL_MOD_CONF_CTRL_0
  98        str     r1, [r0]
  99
 100        /* Move to 1510 mode */
 101        ldr     r0, REG_COMP_MODE_CTRL_0
 102        ldr     r1, VAL_COMP_MODE_CTRL_0
 103        str     r1, [r0]
 104
 105        /* Set up Traffic Ctlr*/
 106        ldr r0, REG_TC_IMIF_PRIO
 107        mov r1, #0x0
 108        str r1, [r0]
 109        ldr r0, REG_TC_EMIFS_PRIO
 110        str r1, [r0]
 111        ldr r0, REG_TC_EMIFF_PRIO
 112        str r1, [r0]
 113
 114        ldr r0, REG_TC_EMIFS_CONFIG
 115        ldr r1, [r0]
 116        bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
 117        bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
 118        str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
 119
 120        /* Setup some clock domains */
 121        ldr r1, =OMAP1510_CLKS
 122        ldr r0, REG_ARM_IDLECT2
 123        strh r1, [r0]  /* CLKM, Clock domain control. */
 124
 125        mov r1, #0x01  /* PER_EN bit */
 126        ldr r0, REG_ARM_RSTCT2
 127        strh r1, [r0]  /* CLKM; Peripheral reset. */
 128
 129        /* Set CLKM to Sync-Scalable  */
 130        /* I supposidly need to enable the dsp clock before switching */
 131        mov r1, #0x1000
 132        ldr r0, REG_ARM_SYSST
 133        strh r1, [r0]
 134        mov r0, #0x400
 1351:
 136        subs r0, r0, #0x1   /* wait for any bubbles to finish */
 137        bne 1b
 138
 139        ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
 140        ldr r0, REG_ARM_CKCTL
 141        strh r1, [r0]
 142
 143        /* setup DPLL 1 */
 144        ldr r1, VAL_DPLL1_CTL
 145        ldr r0, REG_DPLL1_CTL
 146        strh r1, [r0]
 147        ands r1, r1, #0x10  /* Check if PLL is enabled. */
 148        beq lock_end        /* Do not look for lock if BYPASS selected */
 1492:
 150        ldrh r1, [r0]
 151        ands r1, r1, #0x01  /* Check the LOCK bit. */
 152        beq 2b              /* ...loop until bit goes hi. */
 153lock_end:
 154
 155        /* Set memory timings corresponding to the new clock speed */
 156
 157        /* Check execution location to determine current execution location
 158         * and branch to appropriate initialization code.
 159         */
 160        mov r0, #0x10000000                 /* Load physical SDRAM base. */
 161        mov r1, pc                          /* Get current execution location. */
 162        /* Zero all but top 6 bits of PC, as they alone detect whether an
 163         * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
 164         * valid range for SDRAM on the OMAP 1510/5910.
 165         */
 166        and r1, r1, #0xfc000000
 167        cmp r1, r0                      /* Compare. */
 168        beq skip_sdram                  /* Skip over EMIF-fast initialization
 169                                         * if running from SDRAM.
 170                                         */
 171
 172        /*
 173         * Delay for SDRAM initialization.
 174         */
 175        mov r3, #0x1800                        /* value should be checked */
 1763:
 177        subs r3, r3, #0x1                     /* Decrement count */
 178        bne 3b
 179
 180        /*
 181         * Set SDRAM control values. Disable refresh before MRS command.
 182         */
 183        ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
 184        bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
 185        orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
 186        orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
 187        ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
 188        str r3, [r2]                        /* Store the passed value with AR disabled. */
 189
 190        ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
 191        ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
 192        str r1, [r2]                        /* Store the passed value.*/
 193
 194        ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
 195        str r0, [r2]                        /* Store the passed value. */
 196
 197        /*
 198         * Delay for SDRAM initialization.
 199         */
 200        mov r3, #0x1800
 2014:
 202        subs r3, r3, #1                     /* Decrement count. */
 203        bne 4b
 204
 205skip_sdram:
 206
 207        /* slow interface */
 208        ldr r1, VAL_TC_EMIFS_CS0_CONFIG
 209        ldr r0, REG_TC_EMIFS_CS0_CONFIG
 210        str r1, [r0] /* Chip Select 0 */
 211        ldr r1, VAL_TC_EMIFS_CS1_CONFIG
 212        ldr r0, REG_TC_EMIFS_CS1_CONFIG
 213        str r1, [r0] /* Chip Select 1 */
 214        ldr r1, VAL_TC_EMIFS_CS2_CONFIG
 215        ldr r0, REG_TC_EMIFS_CS2_CONFIG
 216        str r1, [r0] /* Chip Select 2 */
 217        ldr r1, VAL_TC_EMIFS_CS3_CONFIG
 218        ldr r0, REG_TC_EMIFS_CS3_CONFIG
 219        str r1, [r0] /* Chip Select 3 */
 220
 221 /* Next, Enable the RS232 Line Drivers in the FPGA. */
 222 /* Also, power on the audio CODEC's amplifier here, */
 223 /* which will make a noise on the audio output. */
 224 /* This is done here instead of in the kernel so there */
 225 /* isn't a loud popping noise at the start of each */
 226 /* song. */
 227 /* Also, disable the CODEC's clocks. */
 228 /* omap1510-HelenP1 [specific] */
 229
 230        ldr r0, REG_FPGA_POWER
 231        mov r1, #0
 232        ldr r2, REG_FPGA_DIP_SWITCH
 233        ldrb r3, [r2]
 234        cmp r3, #0x8
 235        movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
 236        strb r1, [r0]
 237        ldr r0, REG_FPGA_AUDIO
 238        mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
 239        strb r1, [r0]
 240
 241        /* back to arch calling code */
 242        mov     pc, lr
 243
 244/* the literal pools origin */
 245        .ltorg
 246
 247/* OMAP configuration registers */
 248REG_FUNC_MUX_CTRL_0:            /* 32 bits */
 249        .word 0xfffe1000
 250REG_FUNC_MUX_CTRL_1:            /* 32 bits */
 251        .word 0xfffe1004
 252REG_FUNC_MUX_CTRL_2:            /* 32 bits */
 253        .word 0xfffe1008
 254REG_COMP_MODE_CTRL_0:           /* 32 bits */
 255        .word 0xfffe100c
 256REG_FUNC_MUX_CTRL_3:            /* 32 bits */
 257        .word 0xfffe1010
 258REG_FUNC_MUX_CTRL_4:            /* 32 bits */
 259        .word 0xfffe1014
 260REG_FUNC_MUX_CTRL_5:            /* 32 bits */
 261        .word 0xfffe1018
 262REG_FUNC_MUX_CTRL_6:            /* 32 bits */
 263        .word 0xfffe101c
 264REG_FUNC_MUX_CTRL_7:            /* 32 bits */
 265        .word 0xfffe1020
 266REG_FUNC_MUX_CTRL_8:            /* 32 bits */
 267        .word 0xfffe1024
 268REG_FUNC_MUX_CTRL_9:            /* 32 bits */
 269        .word 0xfffe1028
 270REG_FUNC_MUX_CTRL_A:            /* 32 bits */
 271        .word 0xfffe102C
 272REG_FUNC_MUX_CTRL_B:            /* 32 bits */
 273        .word 0xfffe1030
 274REG_FUNC_MUX_CTRL_C:            /* 32 bits */
 275        .word 0xfffe1034
 276REG_FUNC_MUX_CTRL_D:            /* 32 bits */
 277        .word 0xfffe1038
 278REG_PULL_DWN_CTRL_0:            /* 32 bits */
 279        .word 0xfffe1040
 280REG_PULL_DWN_CTRL_1:            /* 32 bits */
 281        .word 0xfffe1044
 282REG_PULL_DWN_CTRL_2:            /* 32 bits */
 283        .word 0xfffe1048
 284REG_PULL_DWN_CTRL_3:            /* 32 bits */
 285        .word 0xfffe104c
 286REG_VOLTAGE_CTRL_0:             /* 32 bits */
 287        .word 0xfffe1060
 288REG_TEST_DBG_CTRL_0:            /* 32 bits */
 289        .word 0xfffe1070
 290REG_MOD_CONF_CTRL_0:            /* 32 bits */
 291        .word 0xfffe1080
 292REG_TC_IMIF_PRIO:               /* 32 bits */
 293        .word 0xfffecc00
 294REG_TC_EMIFS_PRIO:              /* 32 bits */
 295        .word 0xfffecc04
 296REG_TC_EMIFF_PRIO:              /* 32 bits */
 297        .word 0xfffecc08
 298REG_TC_EMIFS_CONFIG:            /* 32 bits */
 299        .word 0xfffecc0c
 300REG_TC_EMIFS_CS0_CONFIG:        /* 32 bits */
 301        .word 0xfffecc10
 302REG_TC_EMIFS_CS1_CONFIG:        /* 32 bits */
 303        .word 0xfffecc14
 304REG_TC_EMIFS_CS2_CONFIG:        /* 32 bits */
 305        .word 0xfffecc18
 306REG_TC_EMIFS_CS3_CONFIG:        /* 32 bits */
 307        .word 0xfffecc1c
 308REG_TC_EMIFF_SDRAM_CONFIG:      /* 32 bits */
 309        .word 0xfffecc20
 310REG_TC_EMIFF_MRS:               /* 32 bits */
 311        .word 0xfffecc24
 312/* MPU clock/reset/power mode control registers */
 313REG_ARM_CKCTL:                  /* 16 bits */
 314        .word 0xfffece00
 315REG_ARM_IDLECT2:                /* 16 bits */
 316        .word 0xfffece08
 317REG_ARM_RSTCT2:                 /* 16 bits */
 318        .word 0xfffece14
 319REG_ARM_SYSST:                  /* 16 bits */
 320        .word 0xfffece18
 321/* DPLL control registers */
 322REG_DPLL1_CTL:                  /* 16 bits */
 323        .word 0xfffecf00
 324/* identification code register */
 325REG_IDCODE:                     /* 32 bits */
 326        .word 0xfffed404
 327
 328/* Innovator specific */
 329REG_FPGA_LED_DIGIT:             /* 8 bits (not used on Innovator) */
 330        .word 0x08000003
 331REG_FPGA_POWER:                 /* 8 bits */
 332        .word 0x08000005
 333REG_FPGA_AUDIO:                 /* 8 bits (not used on Innovator) */
 334        .word 0x0800000c
 335REG_FPGA_DIP_SWITCH:            /* 8 bits (not used on Innovator) */
 336        .word 0x0800000e
 337
 338VAL_COMP_MODE_CTRL_0:
 339        .word 0x0000eaef
 340VAL_FUNC_MUX_CTRL_4:
 341        .word 0x00000000
 342VAL_FUNC_MUX_CTRL_5:
 343        .word 0x00000000
 344VAL_FUNC_MUX_CTRL_6:
 345        .word 0x00000001
 346VAL_FUNC_MUX_CTRL_7:
 347        .word 0x00000000
 348VAL_FUNC_MUX_CTRL_8:
 349        .word 0x10001200
 350VAL_FUNC_MUX_CTRL_9:
 351        .word 0x01201012
 352VAL_FUNC_MUX_CTRL_A:
 353        .word 0x00000248
 354VAL_FUNC_MUX_CTRL_B:
 355        .word 0x00000248
 356VAL_FUNC_MUX_CTRL_C:
 357        .word 0x09000000
 358VAL_FUNC_MUX_CTRL_D:
 359        .word 0x00000000
 360VAL_PULL_DWN_CTRL_0:
 361        .word 0x11a10000
 362VAL_PULL_DWN_CTRL_1:
 363        .word 0x2e047fff
 364VAL_PULL_DWN_CTRL_2:
 365        .word 0xffd603a6
 366VAL_PULL_DWN_CTRL_3:
 367        .word 0x00003e03
 368VAL_VOLTAGE_CTRL_0:
 369        .word 0x00000007
 370VAL_TEST_DBG_CTRL_0:
 371        /*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
 372         *   This slows down internal SRAM accesses.
 373         */
 374        .word 0x00000007
 375VAL_MOD_CONF_CTRL_0:
 376        .word 0x0b000008
 377VAL_ARM_CKCTL:
 378        .word 0x010f
 379VAL_DPLL1_CTL:
 380        .word 0x2710
 381VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
 382        .word 0x00001149
 383VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
 384        .word 0x00004158
 385VAL_TC_EMIFS_CS0_CONFIG:
 386        .word 0x002130b0
 387VAL_TC_EMIFS_CS1_CONFIG:
 388        .word 0x0000f559
 389VAL_TC_EMIFS_CS2_CONFIG:
 390        .word 0x000055f0
 391VAL_TC_EMIFS_CS3_CONFIG:
 392        .word 0x00003331
 393VAL_TC_EMIFF_SDRAM_CONFIG:
 394        .word 0x010290fc
 395VAL_TC_EMIFF_MRS:
 396        .word 0x00000027
 397