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36#include <common.h>
37#include <74xx_7xx.h>
38#include "../../Marvell/include/memory.h"
39#include "../../Marvell/include/pci.h"
40#include "../../Marvell/include/mv_gen_reg.h"
41#include <net.h>
42#include <i2c.h>
43
44#include "eth.h"
45#include "mpsc.h"
46#include "64460.h"
47#include "mv_regs.h"
48#include "p3mx.h"
49
50DECLARE_GLOBAL_DATA_PTR;
51
52#undef DEBUG
53
54
55#ifdef CONFIG_PCI
56#define MAP_PCI
57#endif
58
59#ifdef DEBUG
60#define DP(x) x
61#else
62#define DP(x)
63#endif
64
65extern flash_info_t flash_info[];
66
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73
74
75
76
77
78void board_prebootm_init (void);
79unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
80int display_mem_map (void);
81void set_led(int);
82
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91
92
93void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
94{
95 u32 temp;
96
97
98 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
99 if ((temp & 0xffff) == new_loc >> 16)
100 return;
101
102 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
103 0xffff0000) | (new_loc >> 16);
104
105 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
106
107 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
108}
109
110#ifdef CONFIG_PCI
111
112static void gt_pci_config (void)
113{
114 unsigned int stat;
115 unsigned int val = 0x00fff864;
116
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118
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120
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122
123
124
125 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {
126 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
127
128 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
129
130 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
131 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
132 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
133
134 }
135 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {
136 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
137 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
138
139 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
140 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
141 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
142 }
143
144
145 PCI_MASTER_ENABLE (0, SELF);
146 PCI_MASTER_ENABLE (1, SELF);
147
148
149 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
150 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
151 (1 << 18);
152 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
153 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
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159
160 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
161 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
162 GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
163
164 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
165 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
166 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
167
168 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
169 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
170 GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
171
172 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
173 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
174 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
175
176
177
178 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
179 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
180
181
182 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
183 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
184
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186
187
188#ifdef MAP_PCI
189 for (stat = 0; stat <= PCI_HOST1; stat++)
190 pciWriteConfigReg (stat,
191 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
192 SELF, CONFIG_SYS_GT_REGS);
193#endif
194
195}
196#endif
197
198
199static void gt_cpu_config (void)
200{
201 cpu_t cpu = get_cpu_type ();
202 ulong tmp;
203
204
205 tmp = GTREGREAD (CPU_CONFIGURATION);
206
207#ifndef CONFIG_SYS_GT_DUAL_CPU
208 tmp |= CPU_CONF_SINGLE_CPU;
209#endif
210 tmp &= ~CPU_CONF_AACK_DELAY_2;
211 tmp |= CPU_CONF_DP_VALID;
212 tmp |= CPU_CONF_AP_VALID;
213 tmp |= CPU_CONF_PIPELINE;
214 GT_REG_WRITE (CPU_CONFIGURATION, tmp);
215
216
217 tmp = GTREGREAD (CPU_MASTER_CONTROL);
218 tmp |= CPU_MAST_CTL_ARB_EN;
219
220 if ((cpu == CPU_7400) ||
221 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
222
223 tmp |= CPU_MAST_CTL_CLEAN_BLK;
224 tmp |= CPU_MAST_CTL_FLUSH_BLK;
225
226 } else {
227
228
229
230 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
231 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
232 }
233 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
234}
235
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240
241int board_early_init_f (void)
242{
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249 my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
250
251#ifdef CONFIG_PCI
252 gt_pci_config ();
253#endif
254
255 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
256 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
257
258 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
259 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
260
261 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
262 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
263 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
264 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
265
266
267
268 memoryMapDeviceSpace(DEVICE0, 0, 0);
269 GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
270 memoryMapDeviceSpace(DEVICE1, 0, 0);
271 GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
272 memoryMapDeviceSpace(DEVICE2, 0, 0);
273 GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
274 memoryMapDeviceSpace(DEVICE3, 0, 0);
275 GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
276
277 GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR);
278
279 gt_cpu_config();
280
281
282 GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
283 GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
284 GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
285 GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
286
287 GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
288
289 set_led(LED_RED);
290
291 return 0;
292}
293
294
295
296int misc_init_r ()
297{
298 u8 val;
299
300 icache_enable ();
301#ifdef CONFIG_SYS_L2
302 l2cache_enable ();
303#endif
304#ifdef CONFIG_MPSC
305 mpsc_sdma_init ();
306 mpsc_init2 ();
307#endif
308
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312
313 val = 0xa5;
314 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1);
315
316 return 0;
317}
318
319int board_early_init_r(void)
320{
321
322 mpsc_putchar += gd->reloc_off;
323 mpsc_getchar += gd->reloc_off;
324 mpsc_test_char += gd->reloc_off;
325
326 return 0;
327}
328
329void after_reloc (ulong dest_addr, gd_t * gd)
330{
331 memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
332
333
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335
336 set_led(LED_GREEN);
337 board_init_r (gd, dest_addr);
338
339}
340
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344
345
346int checkboard (void)
347{
348 char *s = getenv("serial#");
349
350 printf("Board: %s", CONFIG_SYS_BOARD_NAME);
351
352 if (s != NULL) {
353 puts(", serial# ");
354 puts(s);
355 }
356 putc('\n');
357
358 return (0);
359}
360
361void set_led(int col)
362{
363 int tmp;
364 int on_pin;
365 int off_pin;
366
367
368
369
370 tmp = GTREGREAD(MPP_CONTROL2);
371 tmp &= 0x00ffffff;
372 GT_REG_WRITE(MPP_CONTROL2,tmp);
373
374
375
376 tmp = GTREGREAD(GPP_IO_CONTROL);
377 tmp |= 0x00C00000;
378 GT_REG_WRITE(GPP_IO_CONTROL, tmp);
379
380
381
382 tmp = GTREGREAD(GPP_LEVEL_CONTROL);
383 tmp &= 0xff3fffff;
384 GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
385
386 switch(col) {
387 default:
388 case LED_OFF :
389 on_pin = 0;
390 off_pin = ((1 << 23) | (1 << 22));
391 break;
392 case LED_RED :
393 on_pin = (1 << 23);
394 off_pin = (1 << 22);
395 break;
396 case LED_GREEN :
397 on_pin = (1 << 22);
398 off_pin = (1 << 23);
399 break;
400 case LED_ORANGE :
401 on_pin = ((1 << 23) | (1 << 22));
402 off_pin = 0;
403 break;
404 }
405
406
407
408 tmp = GTREGREAD(GPP_VALUE);
409 tmp |= on_pin;
410 tmp &= ~off_pin;
411 GT_REG_WRITE(GPP_VALUE, tmp);
412}
413
414int display_mem_map (void)
415{
416 int i;
417 unsigned int base, size, width;
418#ifdef CONFIG_PCI
419 int j;
420#endif
421
422
423 printf ("SD (DDR) RAM\n");
424 for (i = 0; i <= BANK3; i++) {
425 base = memoryGetBankBaseAddress (i);
426 size = memoryGetBankSize (i);
427 if (size != 0)
428 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
429 i, base, size >> 20);
430 }
431#ifdef CONFIG_PCI
432
433 for (i = 0; i <= PCI_HOST1; i++) {
434 printf ("\nCPU's PCI %d windows\n", i);
435 base = pciGetSpaceBase (i, PCI_IO);
436 size = pciGetSpaceSize (i, PCI_IO);
437 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
438 size >> 20);
439
440 for (j = 0; j <= PCI_REGION0; j++) {
441 base = pciGetSpaceBase (i, j);
442 size = pciGetSpaceSize (i, j);
443 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",
444 j, base, size >> 20);
445 }
446 }
447#endif
448
449
450 base = memoryGetDeviceBaseAddress (BOOT_DEVICE);
451 size = memoryGetDeviceSize (BOOT_DEVICE);
452 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
453 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
454 base, size >> 20, width);
455
456 return (0);
457}
458
459
460
461#if defined (CONFIG_SYS_DRAM_TEST)
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483static void move64 (unsigned long long *src, unsigned long long *dest)
484{
485 asm ("lfd 0, 0(3)\n\t"
486 "stfd 0, 0(4)"
487 : : : "fr0");
488 return;
489}
490
491
492#if defined (CONFIG_SYS_DRAM_TEST_DATA)
493
494unsigned long long pattern[] = {
495 0xaaaaaaaaaaaaaaaaULL,
496 0xccccccccccccccccULL,
497 0xf0f0f0f0f0f0f0f0ULL,
498 0xff00ff00ff00ff00ULL,
499 0xffff0000ffff0000ULL,
500 0xffffffff00000000ULL,
501 0x00000000ffffffffULL,
502 0x0000ffff0000ffffULL,
503 0x00ff00ff00ff00ffULL,
504 0x0f0f0f0f0f0f0f0fULL,
505 0x3333333333333333ULL,
506 0x5555555555555555ULL
507};
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553int mem_test_data (void)
554{
555 unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
556 unsigned long long temp64 = 0;
557 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
558 int i;
559 unsigned int hi, lo;
560
561 for (i = 0; i < num_patterns; i++) {
562 move64 (&(pattern[i]), pmem);
563 move64 (pmem, &temp64);
564
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566
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568
569 hi = (pattern[i] >> 32) & 0xffffffff;
570 lo = pattern[i] & 0xffffffff;
571
572
573 if (temp64 != pattern[i]) {
574 printf ("\n Data Test Failed, pattern 0x%08x%08x",
575 hi, lo);
576 return 1;
577 }
578 }
579
580 return 0;
581}
582#endif
583
584#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
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606int mem_test_address (void)
607{
608 volatile unsigned int *pmem =
609 (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
610 const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
611 unsigned int i;
612
613
614 for (i = 0; i < size; i++)
615 pmem[i] = i;
616
617
618 for (i = 0; i < size; i++) {
619 if (pmem[i] != i) {
620 printf ("\n Address Test Failed at 0x%x", i);
621 return 1;
622 }
623 }
624 return 0;
625}
626#endif
627
628#if defined (CONFIG_SYS_DRAM_TEST_WALK)
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656int mem_march (volatile unsigned long long *base,
657 unsigned int size,
658 unsigned long long rmask,
659 unsigned long long wmask, short read, short write)
660{
661 unsigned int i;
662 unsigned long long temp = 0;
663 unsigned int hitemp, lotemp, himask, lomask;
664
665 for (i = 0; i < size; i++) {
666 if (read != 0) {
667
668 move64 ((unsigned long long *) &(base[i]), &temp);
669 if (rmask != temp) {
670 hitemp = (temp >> 32) & 0xffffffff;
671 lotemp = temp & 0xffffffff;
672 himask = (rmask >> 32) & 0xffffffff;
673 lomask = rmask & 0xffffffff;
674
675 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
676 return 1;
677 }
678 }
679 if (write != 0) {
680
681 move64 (&wmask, (unsigned long long *) &(base[i]));
682 }
683 }
684 return 0;
685}
686#endif
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714int mem_test_walk (void)
715{
716 unsigned long long mask;
717 volatile unsigned long long *pmem =
718 (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
719 const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
720
721 unsigned int i;
722
723 mask = 0x01;
724
725 printf ("Initial Pass");
726 mem_march (pmem, size, 0x0, 0x1, 0, 1);
727
728 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
729 printf (" ");
730 printf (" ");
731 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
732
733 for (i = 0; i < 63; i++) {
734 printf ("Pass %2d", i + 2);
735 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
736
737 return 1;
738 }
739 mask = mask << 1;
740 printf ("\b\b\b\b\b\b\b");
741 }
742
743 printf ("Last Pass");
744 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
745
746 return 1;
747 }
748 printf ("\b\b\b\b\b\b\b\b\b");
749 printf (" ");
750 printf ("\b\b\b\b\b\b\b\b\b");
751
752 return 0;
753}
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778int testdram (void)
779{
780 char *s;
781 int rundata = 0;
782 int runaddress = 0;
783 int runwalk = 0;
784
785#ifdef CONFIG_SYS_DRAM_TEST_DATA
786 s = getenv ("testdramdata");
787 rundata = (s && (*s == 'y')) ? 1 : 0;
788#endif
789#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
790 s = getenv ("testdramaddress");
791 runaddress = (s && (*s == 'y')) ? 1 : 0;
792#endif
793#ifdef CONFIG_SYS_DRAM_TEST_WALK
794 s = getenv ("testdramwalk");
795 runwalk = (s && (*s == 'y')) ? 1 : 0;
796#endif
797
798 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
799 printf ("Testing RAM from 0x%08x to 0x%08x ... "
800 "(don't panic... that will take a moment !!!!)\n",
801 CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
802#ifdef CONFIG_SYS_DRAM_TEST_DATA
803 if (rundata == 1) {
804 printf ("Test DATA ... ");
805 if (mem_test_data () == 1) {
806 printf ("failed \n");
807 return 1;
808 } else
809 printf ("ok \n");
810 }
811#endif
812#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
813 if (runaddress == 1) {
814 printf ("Test ADDRESS ... ");
815 if (mem_test_address () == 1) {
816 printf ("failed \n");
817 return 1;
818 } else
819 printf ("ok \n");
820 }
821#endif
822#ifdef CONFIG_SYS_DRAM_TEST_WALK
823 if (runwalk == 1) {
824 printf ("Test WALKING ONEs ... ");
825 if (mem_test_walk () == 1) {
826 printf ("failed \n");
827 return 1;
828 } else
829 printf ("ok \n");
830 }
831#endif
832 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
833 printf ("passed\n");
834 return 0;
835
836}
837#endif
838
839
840
841
842
843
844void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
845{
846 u32 temp;
847
848 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
849 if ((temp & 0xffff) == new_loc >> 16)
850 return;
851
852 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
853 0xffff0000) | (new_loc >> 16);
854
855 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
856
857 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
858 new_loc |
859 (INTERNAL_SPACE_DECODE)))))
860 != temp);
861
862}
863