LXR uboot/cpu/arm926ejs/at91/at91sam9261

   1/*
   2 * (C) Copyright 2007-2008
   3 * Stelian Pop <stelian.pop@leadtechdesign.com>
   4 * Lead Tech Design <www.leadtechdesign.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <common.h>
  26#include <asm/arch/at91_common.h>
  27#include <asm/arch/at91_pmc.h>
  28#include <asm/arch/gpio.h>
  29#include <asm/arch/io.h>
  30
  31void at91_serial0_hw_init(void)
  32{
  33        at91_set_A_periph(AT91_PIN_PC8, 1);             /* TXD0 */
  34        at91_set_A_periph(AT91_PIN_PC9, 0);             /* RXD0 */
  35        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
  36}
  37
  38void at91_serial1_hw_init(void)
  39{
  40        at91_set_A_periph(AT91_PIN_PC12, 1);            /* TXD1 */
  41        at91_set_A_periph(AT91_PIN_PC13, 0);            /* RXD1 */
  42        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
  43}
  44
  45void at91_serial2_hw_init(void)
  46{
  47        at91_set_A_periph(AT91_PIN_PC14, 1);            /* TXD2 */
  48        at91_set_A_periph(AT91_PIN_PC15, 0);            /* RXD2 */
  49        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
  50}
  51
  52void at91_serial3_hw_init(void)
  53{
  54        at91_set_A_periph(AT91_PIN_PA9, 0);             /* DRXD */
  55        at91_set_A_periph(AT91_PIN_PA10, 1);            /* DTXD */
  56        at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
  57}
  58
  59void at91_serial_hw_init(void)
  60{
  61#ifdef CONFIG_USART0
  62        at91_serial0_hw_init();
  63#endif
  64
  65#ifdef CONFIG_USART1
  66        at91_serial1_hw_init();
  67#endif
  68
  69#ifdef CONFIG_USART2
  70        at91_serial2_hw_init();
  71#endif
  72
  73#ifdef CONFIG_USART3    /* DBGU */
  74        at91_serial3_hw_init();
  75#endif
  76}
  77
  78#ifdef CONFIG_HAS_DATAFLASH
  79void at91_spi0_hw_init(unsigned long cs_mask)
  80{
  81        at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
  82        at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
  83        at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
  84
  85        /* Enable clock */
  86        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
  87
  88        if (cs_mask & (1 << 0)) {
  89                at91_set_A_periph(AT91_PIN_PA3, 1);
  90        }
  91        if (cs_mask & (1 << 1)) {
  92                at91_set_A_periph(AT91_PIN_PA4, 1);
  93        }
  94        if (cs_mask & (1 << 2)) {
  95                at91_set_A_periph(AT91_PIN_PA5, 1);
  96        }
  97        if (cs_mask & (1 << 3)) {
  98                at91_set_A_periph(AT91_PIN_PA6, 1);
  99        }
 100        if (cs_mask & (1 << 4)) {
 101                at91_set_gpio_output(AT91_PIN_PA3, 1);
 102        }
 103        if (cs_mask & (1 << 5)) {
 104                at91_set_gpio_output(AT91_PIN_PA4, 1);
 105        }
 106        if (cs_mask & (1 << 6)) {
 107                at91_set_gpio_output(AT91_PIN_PA5, 1);
 108        }
 109        if (cs_mask & (1 << 7)) {
 110                at91_set_gpio_output(AT91_PIN_PA6, 1);
 111        }
 112}
 113
 114void at91_spi1_hw_init(unsigned long cs_mask)
 115{
 116        at91_set_A_periph(AT91_PIN_PB30, 0);    /* SPI1_MISO */
 117        at91_set_A_periph(AT91_PIN_PB31, 0);    /* SPI1_MOSI */
 118        at91_set_A_periph(AT91_PIN_PB29, 0);    /* SPI1_SPCK */
 119
 120        /* Enable clock */
 121        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1);
 122
 123        if (cs_mask & (1 << 0)) {
 124                at91_set_A_periph(AT91_PIN_PB28, 1);
 125        }
 126        if (cs_mask & (1 << 1)) {
 127                at91_set_B_periph(AT91_PIN_PA24, 1);
 128        }
 129        if (cs_mask & (1 << 2)) {
 130                at91_set_B_periph(AT91_PIN_PA25, 1);
 131        }
 132        if (cs_mask & (1 << 3)) {
 133                at91_set_A_periph(AT91_PIN_PA26, 1);
 134        }
 135        if (cs_mask & (1 << 4)) {
 136                at91_set_gpio_output(AT91_PIN_PB28, 1);
 137        }
 138        if (cs_mask & (1 << 5)) {
 139                at91_set_gpio_output(AT91_PIN_PA24, 1);
 140        }
 141        if (cs_mask & (1 << 6)) {
 142                at91_set_gpio_output(AT91_PIN_PA25, 1);
 143        }
 144        if (cs_mask & (1 << 7)) {
 145                at91_set_gpio_output(AT91_PIN_PA26, 1);
 146        }
 147}
 148#endif
 149