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15#include <common.h>
16#include <asm/fsl_ddr_sdram.h>
17
18#include "ddr.h"
19
20extern void fsl_ddr_set_lawbar(
21 const common_timing_params_t *memctl_common_params,
22 unsigned int memctl_interleaved,
23 unsigned int ctrl_num);
24
25
26extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
27 unsigned int ctrl_num);
28
29
30extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
31 unsigned int ctrl_num);
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78#ifdef DEBUG
79const char *step_string_tbl[] = {
80 "STEP_GET_SPD",
81 "STEP_COMPUTE_DIMM_PARMS",
82 "STEP_COMPUTE_COMMON_PARMS",
83 "STEP_GATHER_OPTS",
84 "STEP_ASSIGN_ADDRESSES",
85 "STEP_COMPUTE_REGS",
86 "STEP_PROGRAM_REGS",
87 "STEP_ALL"
88};
89
90const char * step_to_string(unsigned int step) {
91
92 unsigned int s = __ilog2(step);
93
94 if ((1 << s) != step)
95 return step_string_tbl[7];
96
97 return step_string_tbl[s];
98}
99#endif
100
101int step_assign_addresses(fsl_ddr_info_t *pinfo,
102 unsigned int dbw_cap_adj[],
103 unsigned int *memctl_interleaving,
104 unsigned int *rank_interleaving)
105{
106 int i, j;
107
108
109
110
111
112
113
114 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
115 unsigned int found = 0;
116
117 switch (pinfo->memctl_opts[i].data_bus_width) {
118 case 2:
119
120 printf("can't handle 16-bit mode yet\n");
121 break;
122
123 case 1:
124
125 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
126 unsigned int dw;
127 dw = pinfo->dimm_params[i][j].data_width;
128 if (pinfo->dimm_params[i][j].n_ranks
129 && (dw == 72 || dw == 64)) {
130
131
132
133
134
135 found = 1;
136 break;
137 }
138 }
139 if (found) {
140 dbw_cap_adj[i] = 1;
141 }
142 break;
143
144 case 0:
145
146 break;
147
148 default:
149 printf("unexpected data bus width "
150 "specified controller %u\n", i);
151 return 1;
152 }
153 }
154
155
156
157
158
159 j = 0;
160 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
161 if (pinfo->memctl_opts[i].memctl_interleaving) {
162 j++;
163 }
164 }
165 if (j == 2)
166 *memctl_interleaving = 1;
167
168
169 j = 0;
170 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
171 if (pinfo->memctl_opts[i].ba_intlv_ctl) {
172 j++;
173 }
174 }
175 if (j == 2)
176 *rank_interleaving = 1;
177
178 if (*memctl_interleaving) {
179 unsigned long long addr, total_mem_per_ctlr = 0;
180
181
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193
194
195 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
196 addr = 0;
197 pinfo->common_timing_params[i].base_address = 0ull;
198 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
199 unsigned long long cap
200 = pinfo->dimm_params[i][j].capacity;
201
202 pinfo->dimm_params[i][j].base_address = addr;
203 addr += cap >> dbw_cap_adj[i];
204 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
205 }
206 }
207 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
208 } else {
209
210
211
212
213 unsigned long long cur_memsize = 0;
214 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
215 u64 total_mem_per_ctlr = 0;
216 pinfo->common_timing_params[i].base_address =
217 cur_memsize;
218 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
219
220 unsigned long long cap =
221 pinfo->dimm_params[i][j].capacity;
222 pinfo->dimm_params[i][j].base_address =
223 cur_memsize;
224 cur_memsize += cap >> dbw_cap_adj[i];
225 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
226 }
227 pinfo->common_timing_params[i].total_mem =
228 total_mem_per_ctlr;
229 }
230 }
231
232 return 0;
233}
234
235unsigned long long
236fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
237{
238 unsigned int i, j;
239 unsigned int all_controllers_memctl_interleaving = 0;
240 unsigned int all_controllers_rank_interleaving = 0;
241 unsigned long long total_mem = 0;
242
243 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
244 common_timing_params_t *timing_params = pinfo->common_timing_params;
245
246
247 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
248
249 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
250 dbw_capacity_adjust[i] = 0;
251 }
252
253 debug("starting at step %u (%s)\n",
254 start_step, step_to_string(start_step));
255
256 switch (start_step) {
257 case STEP_GET_SPD:
258
259 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
260 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
261 }
262
263 case STEP_COMPUTE_DIMM_PARMS:
264
265
266 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
267 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
268 unsigned int retval;
269 generic_spd_eeprom_t *spd =
270 &(pinfo->spd_installed_dimms[i][j]);
271 dimm_params_t *pdimm =
272 &(pinfo->dimm_params[i][j]);
273
274 retval = compute_dimm_parameters(spd, pdimm, i);
275 if (retval == 2) {
276 printf("Error: compute_dimm_parameters"
277 " non-zero returned FATAL value "
278 "for memctl=%u dimm=%u\n", i, j);
279 return 0;
280 }
281 if (retval) {
282 debug("Warning: compute_dimm_parameters"
283 " non-zero return value for memctl=%u "
284 "dimm=%u\n", i, j);
285 }
286 }
287 }
288
289 case STEP_COMPUTE_COMMON_PARMS:
290
291
292
293
294 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
295 debug("Computing lowest common DIMM"
296 " parameters for memctl=%u\n", i);
297 compute_lowest_common_dimm_parameters(
298 pinfo->dimm_params[i],
299 &timing_params[i],
300 CONFIG_DIMM_SLOTS_PER_CTLR);
301 }
302
303 case STEP_GATHER_OPTS:
304
305 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
306 debug("Reloading memory controller "
307 "configuration options for memctl=%u\n", i);
308
309
310
311
312
313
314 populate_memctl_options(
315 timing_params[i].all_DIMMs_registered,
316 &pinfo->memctl_opts[i],
317 pinfo->dimm_params[i], i);
318 }
319
320 case STEP_ASSIGN_ADDRESSES:
321
322 step_assign_addresses(pinfo,
323 dbw_capacity_adjust,
324 &all_controllers_memctl_interleaving,
325 &all_controllers_rank_interleaving);
326
327 case STEP_COMPUTE_REGS:
328
329 debug("FSL Memory ctrl cg register computation\n");
330 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
331 if (timing_params[i].ndimms_present == 0) {
332 memset(&ddr_reg[i], 0,
333 sizeof(fsl_ddr_cfg_regs_t));
334 continue;
335 }
336
337 compute_fsl_memctl_config_regs(
338 &pinfo->memctl_opts[i],
339 &ddr_reg[i], &timing_params[i],
340 pinfo->dimm_params[i],
341 dbw_capacity_adjust[i]);
342 }
343
344 default:
345 break;
346 }
347
348
349
350
351
352
353
354
355 if (!all_controllers_memctl_interleaving
356 && all_controllers_rank_interleaving) {
357 total_mem = 0;
358 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
359 total_mem += timing_params[i].total_mem;
360 }
361
362 } else {
363
364
365
366
367
368
369 unsigned int max_end = 0;
370
371 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
372 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
373 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
374 if (reg->cs[j].config & 0x80000000) {
375 unsigned int end;
376 end = reg->cs[j].bnds & 0xFFF;
377 if (end > max_end) {
378 max_end = end;
379 }
380 }
381 }
382 }
383
384 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
385 | 0xFFFFFFULL);
386 }
387
388 return total_mem;
389}
390
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393
394
395
396
397phys_size_t fsl_ddr_sdram(void)
398{
399 unsigned int i;
400 unsigned int memctl_interleaved;
401 unsigned long long total_memory;
402 fsl_ddr_info_t info;
403
404
405 memset(&info, 0, sizeof(fsl_ddr_info_t));
406
407
408 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD);
409
410
411 memctl_interleaved = 0;
412 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
413 memctl_interleaved +=
414 info.memctl_opts[i].memctl_interleaving;
415 }
416
417 if (memctl_interleaved) {
418 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
419 debug("memctl interleaving\n");
420
421
422
423
424 memctl_interleaved = 1;
425 } else {
426 printf("Warning: memctl interleaving not "
427 "properly configured on all controllers\n");
428 memctl_interleaved = 0;
429 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
430 info.memctl_opts[i].memctl_interleaving = 0;
431 debug("Recomputing with memctl_interleaving off.\n");
432 total_memory = fsl_ddr_compute(&info,
433 STEP_ASSIGN_ADDRESSES);
434 }
435 }
436
437
438 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
439 debug("Programming controller %u\n", i);
440 if (info.common_timing_params[i].ndimms_present == 0) {
441 debug("No dimms present on controller %u; "
442 "skipping programming\n", i);
443 continue;
444 }
445
446 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
447 }
448
449 if (memctl_interleaved) {
450 const unsigned int ctrl_num = 0;
451
452
453 fsl_ddr_set_lawbar(&info.common_timing_params[0],
454 memctl_interleaved, ctrl_num);
455 } else {
456
457
458
459
460 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
461 fsl_ddr_set_lawbar(&info.common_timing_params[i],
462 0, i);
463 }
464 }
465
466 debug("total_memory = %llu\n", total_memory);
467
468#if !defined(CONFIG_PHYS_64BIT)
469
470 if (total_memory >= (1ull << 32)) {
471 printf("Detected %lld MB of memory\n", total_memory >> 20);
472 printf("This U-Boot only supports < 4G of DDR\n");
473 printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
474 total_memory = CONFIG_MAX_MEM_MAPPED;
475 }
476#endif
477
478 return total_memory;
479}
480