uboot/include/asm-m68k/coldfire/edma.h
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   1/*
   2 * EDMA Internal Memory Map
   3 *
   4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6 *
   7 * See file CREDITS for list of people who contributed to this
   8 * project.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#ifndef __EDMA_H__
  27#define __EDMA_H__
  28
  29/*********************************************************************
  30* Enhanced DMA (EDMA)
  31*********************************************************************/
  32
  33/* eDMA module registers */
  34typedef struct edma_ctrl {
  35        u32 cr;                 /* 0x00 Control Register */
  36        u32 es;                 /* 0x04 Error Status Register */
  37        u16 res1[3];            /* 0x08 - 0x0D */
  38        u16 erq;                /* 0x0E Enable Request Register */
  39        u16 res2[3];            /* 0x10 - 0x15 */
  40        u16 eei;                /* 0x16 Enable Error Interrupt Request */
  41        u8 serq;                /* 0x18 Set Enable Request */
  42        u8 cerq;                /* 0x19 Clear Enable Request */
  43        u8 seei;                /* 0x1A Set En Error Interrupt Request */
  44        u8 ceei;                /* 0x1B Clear En Error Interrupt Request */
  45        u8 cint;                /* 0x1C Clear Interrupt Enable */
  46        u8 cerr;                /* 0x1D Clear Error */
  47        u8 ssrt;                /* 0x1E Set START Bit */
  48        u8 cdne;                /* 0x1F Clear DONE Status Bit */
  49        u16 res3[3];            /* 0x20 - 0x25 */
  50        u16 intr;               /* 0x26 Interrupt Request */
  51        u16 res4[3];            /* 0x28 - 0x2D */
  52        u16 err;                /* 0x2E Error Register */
  53        u32 res5[52];           /* 0x30 - 0xFF */
  54        u8 dchpri0;             /* 0x100 Channel 0 Priority */
  55        u8 dchpri1;             /* 0x101 Channel 1 Priority */
  56        u8 dchpri2;             /* 0x102 Channel 2 Priority */
  57        u8 dchpri3;             /* 0x103 Channel 3 Priority */
  58        u8 dchpri4;             /* 0x104 Channel 4 Priority */
  59        u8 dchpri5;             /* 0x105 Channel 5 Priority */
  60        u8 dchpri6;             /* 0x106 Channel 6 Priority */
  61        u8 dchpri7;             /* 0x107 Channel 7 Priority */
  62        u8 dchpri8;             /* 0x108 Channel 8 Priority */
  63        u8 dchpri9;             /* 0x109 Channel 9 Priority */
  64        u8 dchpri10;            /* 0x110 Channel 10 Priority */
  65        u8 dchpri11;            /* 0x111 Channel 11 Priority */
  66        u8 dchpri12;            /* 0x112 Channel 12 Priority */
  67        u8 dchpri13;            /* 0x113 Channel 13 Priority */
  68        u8 dchpri14;            /* 0x114 Channel 14 Priority */
  69        u8 dchpri15;            /* 0x115 Channel 15 Priority */
  70} edma_t;
  71
  72/* TCD - eDMA*/
  73typedef struct tcd_ctrl {
  74        u32 saddr;              /* 0x00 Source Address */
  75        u16 attr;               /* 0x04 Transfer Attributes */
  76        u16 soff;               /* 0x06 Signed Source Address Offset */
  77        u32 nbytes;             /* 0x08 Minor Byte Count */
  78        u32 slast;              /* 0x0C Last Source Address Adjustment */
  79        u32 daddr;              /* 0x10 Destination address */
  80        u16 citer;              /* 0x14 Cur Minor Loop Link, Major Loop Cnt */
  81        u16 doff;               /* 0x16 Signed Destination Address Offset */
  82        u32 dlast_sga;          /* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
  83        u16 biter;              /* 0x1C Minor Loop Lnk, Major Loop Cnt */
  84        u16 csr;                /* 0x1E Control and Status */
  85} tcd_st;
  86
  87typedef struct tcd_multiple {
  88        tcd_st tcd[16];
  89} tcd_t;
  90
  91/* Bit definitions and macros for EPPAR */
  92#define EPORT_EPPAR_EPPA1(x)            (((x)&0x0003)<<2)
  93#define EPORT_EPPAR_EPPA2(x)            (((x)&0x0003)<<4)
  94#define EPORT_EPPAR_EPPA3(x)            (((x)&0x0003)<<6)
  95#define EPORT_EPPAR_EPPA4(x)            (((x)&0x0003)<<8)
  96#define EPORT_EPPAR_EPPA5(x)            (((x)&0x0003)<<10)
  97#define EPORT_EPPAR_EPPA6(x)            (((x)&0x0003)<<12)
  98#define EPORT_EPPAR_EPPA7(x)            (((x)&0x0003)<<14)
  99#define EPORT_EPPAR_LEVEL               (0)
 100#define EPORT_EPPAR_RISING              (1)
 101#define EPORT_EPPAR_FALLING             (2)
 102#define EPORT_EPPAR_BOTH                (3)
 103#define EPORT_EPPAR_EPPA7_LEVEL         (0x0000)
 104#define EPORT_EPPAR_EPPA7_RISING        (0x4000)
 105#define EPORT_EPPAR_EPPA7_FALLING       (0x8000)
 106#define EPORT_EPPAR_EPPA7_BOTH          (0xC000)
 107#define EPORT_EPPAR_EPPA6_LEVEL         (0x0000)
 108#define EPORT_EPPAR_EPPA6_RISING        (0x1000)
 109#define EPORT_EPPAR_EPPA6_FALLING       (0x2000)
 110#define EPORT_EPPAR_EPPA6_BOTH          (0x3000)
 111#define EPORT_EPPAR_EPPA5_LEVEL         (0x0000)
 112#define EPORT_EPPAR_EPPA5_RISING        (0x0400)
 113#define EPORT_EPPAR_EPPA5_FALLING       (0x0800)
 114#define EPORT_EPPAR_EPPA5_BOTH          (0x0C00)
 115#define EPORT_EPPAR_EPPA4_LEVEL         (0x0000)
 116#define EPORT_EPPAR_EPPA4_RISING        (0x0100)
 117#define EPORT_EPPAR_EPPA4_FALLING       (0x0200)
 118#define EPORT_EPPAR_EPPA4_BOTH          (0x0300)
 119#define EPORT_EPPAR_EPPA3_LEVEL         (0x0000)
 120#define EPORT_EPPAR_EPPA3_RISING        (0x0040)
 121#define EPORT_EPPAR_EPPA3_FALLING       (0x0080)
 122#define EPORT_EPPAR_EPPA3_BOTH          (0x00C0)
 123#define EPORT_EPPAR_EPPA2_LEVEL         (0x0000)
 124#define EPORT_EPPAR_EPPA2_RISING        (0x0010)
 125#define EPORT_EPPAR_EPPA2_FALLING       (0x0020)
 126#define EPORT_EPPAR_EPPA2_BOTH          (0x0030)
 127#define EPORT_EPPAR_EPPA1_LEVEL         (0x0000)
 128#define EPORT_EPPAR_EPPA1_RISING        (0x0004)
 129#define EPORT_EPPAR_EPPA1_FALLING       (0x0008)
 130#define EPORT_EPPAR_EPPA1_BOTH          (0x000C)
 131
 132/* Bit definitions and macros for EPDDR */
 133#define EPORT_EPDDR_EPDD1               (0x02)
 134#define EPORT_EPDDR_EPDD2               (0x04)
 135#define EPORT_EPDDR_EPDD3               (0x08)
 136#define EPORT_EPDDR_EPDD4               (0x10)
 137#define EPORT_EPDDR_EPDD5               (0x20)
 138#define EPORT_EPDDR_EPDD6               (0x40)
 139#define EPORT_EPDDR_EPDD7               (0x80)
 140
 141/* Bit definitions and macros for EPIER */
 142#define EPORT_EPIER_EPIE1               (0x02)
 143#define EPORT_EPIER_EPIE2               (0x04)
 144#define EPORT_EPIER_EPIE3               (0x08)
 145#define EPORT_EPIER_EPIE4               (0x10)
 146#define EPORT_EPIER_EPIE5               (0x20)
 147#define EPORT_EPIER_EPIE6               (0x40)
 148#define EPORT_EPIER_EPIE7               (0x80)
 149
 150/* Bit definitions and macros for EPDR */
 151#define EPORT_EPDR_EPD1                 (0x02)
 152#define EPORT_EPDR_EPD2                 (0x04)
 153#define EPORT_EPDR_EPD3                 (0x08)
 154#define EPORT_EPDR_EPD4                 (0x10)
 155#define EPORT_EPDR_EPD5                 (0x20)
 156#define EPORT_EPDR_EPD6                 (0x40)
 157#define EPORT_EPDR_EPD7                 (0x80)
 158
 159/* Bit definitions and macros for EPPDR */
 160#define EPORT_EPPDR_EPPD1               (0x02)
 161#define EPORT_EPPDR_EPPD2               (0x04)
 162#define EPORT_EPPDR_EPPD3               (0x08)
 163#define EPORT_EPPDR_EPPD4               (0x10)
 164#define EPORT_EPPDR_EPPD5               (0x20)
 165#define EPORT_EPPDR_EPPD6               (0x40)
 166#define EPORT_EPPDR_EPPD7               (0x80)
 167
 168/* Bit definitions and macros for EPFR */
 169#define EPORT_EPFR_EPF1                 (0x02)
 170#define EPORT_EPFR_EPF2                 (0x04)
 171#define EPORT_EPFR_EPF3                 (0x08)
 172#define EPORT_EPFR_EPF4                 (0x10)
 173#define EPORT_EPFR_EPF5                 (0x20)
 174#define EPORT_EPFR_EPF6                 (0x40)
 175#define EPORT_EPFR_EPF7                 (0x80)
 176
 177#endif                                  /* __EDMA_H__ */
 178