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26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30
31#define CONFIG_BOOKE 1
32#define CONFIG_E500 1
33#define CONFIG_MPC85xx 1
34#define CONFIG_MPC8544 1
35#define CONFIG_MPC8544DS 1
36
37#define CONFIG_PCI 1
38#define CONFIG_PCI1 1
39#define CONFIG_PCIE1 1
40#define CONFIG_PCIE2 1
41#define CONFIG_PCIE3 1
42#define CONFIG_FSL_PCI_INIT 1
43#define CONFIG_FSL_PCIE_RESET 1
44#define CONFIG_SYS_PCI_64BIT 1
45
46#define CONFIG_FSL_LAW 1
47#define CONFIG_E1000 1
48
49#define CONFIG_TSEC_ENET
50#define CONFIG_ENV_OVERWRITE
51#define CONFIG_INTERRUPTS
52
53
54
55
56
57
58#define CONFIG_ASSUME_AMD_FLASH
59
60#ifndef __ASSEMBLY__
61extern unsigned long get_board_sys_clk(unsigned long dummy);
62#endif
63#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
64
65
66
67
68#define CONFIG_L2_CACHE
69#define CONFIG_BTB
70
71
72
73
74#define CONFIG_ENABLE_36BIT_PHYS 1
75
76#define CONFIG_SYS_MEMTEST_START 0x00200000
77#define CONFIG_SYS_MEMTEST_END 0x00400000
78#define CONFIG_PANIC_HANG
79
80
81
82
83
84#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
85#define CONFIG_SYS_CCSRBAR 0xe0000000
86#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
87#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
88
89#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
90#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
91#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
92#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
93
94
95#define CONFIG_FSL_DDR2
96#undef CONFIG_FSL_DDR_INTERACTIVE
97#define CONFIG_SPD_EEPROM
98#define CONFIG_DDR_SPD
99
100#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
101#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
102
103#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
104#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
105#define CONFIG_VERY_BIG_RAM
106
107#define CONFIG_NUM_DDR_CONTROLLERS 1
108#define CONFIG_DIMM_SLOTS_PER_CTLR 1
109#define CONFIG_CHIP_SELECTS_PER_CTRL 2
110
111
112#define SPD_EEPROM_ADDRESS 0x51
113
114
115#ifndef CONFIG_SPD_EEPROM
116#error ("CONFIG_SPD_EEPROM is required")
117#endif
118
119#undef CONFIG_CLOCKS_IN_MHZ
120
121
122
123
124
125
126
127
128
129
130
131
132
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145
146
147
148
149#define CONFIG_SYS_BOOT_BLOCK 0xfc000000
150
151#define CONFIG_SYS_FLASH_BASE 0xff800000
152
153#define CONFIG_SYS_BR0_PRELIM 0xff801001
154#define CONFIG_SYS_BR1_PRELIM 0xfe801001
155
156#define CONFIG_SYS_OR0_PRELIM 0xff806e65
157#define CONFIG_SYS_OR1_PRELIM 0xff806e65
158
159#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
160
161#define CONFIG_SYS_FLASH_QUIET_TEST
162#define CONFIG_SYS_MAX_FLASH_BANKS 1
163#define CONFIG_SYS_MAX_FLASH_SECT 128
164#undef CONFIG_SYS_FLASH_CHECKSUM
165#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
166#define CONFIG_SYS_FLASH_WRITE_TOUT 500
167#define CONFIG_FLASH_SHOW_PROGRESS 45
168
169#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
170
171#define CONFIG_FLASH_CFI_DRIVER
172#define CONFIG_SYS_FLASH_CFI
173#define CONFIG_SYS_FLASH_EMPTY_INFO
174
175#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
176
177#define CONFIG_SYS_BR2_PRELIM 0xf8201001
178#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7
179
180#define CONFIG_SYS_BR3_PRELIM 0xf8100801
181#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7
182
183#define CONFIG_FSL_PIXIS 1
184#define PIXIS_BASE 0xf8100000
185#define PIXIS_ID 0x0
186#define PIXIS_VER 0x1
187#define PIXIS_PVER 0x2
188#define PIXIS_RST 0x4
189#define PIXIS_AUX 0x6
190
191#define PIXIS_SPD 0x7
192#define PIXIS_VCTL 0x10
193#define PIXIS_VCFGEN0 0x12
194#define PIXIS_VCFGEN1 0x13
195#define PIXIS_VBOOT 0x16
196#define PIXIS_VBOOT_FMAP 0x80
197#define PIXIS_VBOOT_FBANK 0x40
198#define PIXIS_VSPEED0 0x17
199#define PIXIS_VSPEED1 0x18
200#define PIXIS_VCLKH 0x19
201#define PIXIS_VCLKL 0x1A
202#define PIXIS_VSPEED2 0x1d
203#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40
204#define PIXIS_VSPEED2_TSEC1SER 0x2
205#define PIXIS_VSPEED2_TSEC3SER 0x1
206#define PIXIS_VCFGEN1_TSEC1SER 0x20
207#define PIXIS_VCFGEN1_TSEC3SER 0x40
208#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
209#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
210
211
212#define CONFIG_SYS_INIT_RAM_LOCK 1
213#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000
214#define CONFIG_SYS_INIT_RAM_END 0x00004000
215
216
217#define CONFIG_SYS_GBL_DATA_SIZE 128
218#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
220
221#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
222#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
223
224
225
226
227
228#define CONFIG_CONS_INDEX 1
229#undef CONFIG_SERIAL_SOFTWARE_FIFO
230#define CONFIG_SYS_NS16550
231#define CONFIG_SYS_NS16550_SERIAL
232#define CONFIG_SYS_NS16550_REG_SIZE 1
233#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
234
235#define CONFIG_SYS_BAUDRATE_TABLE \
236 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
237
238#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
239#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
240
241
242#define CONFIG_SYS_HUSH_PARSER
243#ifdef CONFIG_SYS_HUSH_PARSER
244#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
245#endif
246
247
248#define CONFIG_OF_LIBFDT 1
249#define CONFIG_OF_BOARD_SETUP 1
250#define CONFIG_OF_STDOUT_VIA_ALIAS 1
251
252#define CONFIG_SYS_64BIT_STRTOUL 1
253#define CONFIG_SYS_64BIT_VSPRINTF 1
254
255
256#define CONFIG_FSL_I2C
257#define CONFIG_HARD_I2C
258#undef CONFIG_SOFT_I2C
259#define CONFIG_SYS_I2C_SPEED 400000
260#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
261#define CONFIG_SYS_I2C_SLAVE 0x7F
262#define CONFIG_SYS_I2C_NOPROBES {0x69}
263#define CONFIG_SYS_I2C_OFFSET 0x3100
264
265
266
267
268
269#define CONFIG_SYS_PCIE_VIRT 0x80000000
270#define CONFIG_SYS_PCIE_PHYS 0x80000000
271#define CONFIG_SYS_PCI_VIRT 0xc0000000
272#define CONFIG_SYS_PCI_PHYS 0xc0000000
273
274#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
275#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
276#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
277#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
278#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
279#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
280#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
281#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
282
283
284#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
285#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
286#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
287#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
288#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
289#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
290#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
291#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
292
293
294#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
295#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
296#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
297#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
298#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
299#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
300#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
301#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
302
303
304#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
305#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
306#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
307#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000
308#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000
309#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
310#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000
311#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000
312#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
313#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
314#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
315#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000
316
317#if defined(CONFIG_PCI)
318
319
320#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
321
322
323
324
325
326#define CONFIG_VIDEO
327
328#if defined(CONFIG_VIDEO)
329#define CONFIG_BIOSEMU
330#define CONFIG_CFB_CONSOLE
331#define CONFIG_VIDEO_SW_CURSOR
332#define CONFIG_VGA_AS_SINGLE_DEVICE
333#define CONFIG_ATI_RADEON_FB
334#define CONFIG_VIDEO_LOGO
335
336#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
337#endif
338
339#define CONFIG_NET_MULTI
340#define CONFIG_PCI_PNP
341
342#undef CONFIG_EEPRO100
343#undef CONFIG_TULIP
344#define CONFIG_RTL8139
345
346#ifndef CONFIG_PCI_PNP
347 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
348 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
349 #define PCI_IDSEL_NUMBER 0x11
350#endif
351
352#define CONFIG_PCI_SCAN_SHOW
353#define CONFIG_DOS_PARTITION
354#define CONFIG_SCSI_AHCI
355
356#ifdef CONFIG_SCSI_AHCI
357#define CONFIG_SATA_ULI5288
358#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
359#define CONFIG_SYS_SCSI_MAX_LUN 1
360#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
361#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
362#endif
363
364#endif
365
366
367#if defined(CONFIG_TSEC_ENET)
368
369#ifndef CONFIG_NET_MULTI
370#define CONFIG_NET_MULTI 1
371#endif
372
373#define CONFIG_MII 1
374#define CONFIG_MII_DEFAULT_TSEC 1
375#define CONFIG_TSEC1 1
376#define CONFIG_TSEC1_NAME "eTSEC1"
377#define CONFIG_TSEC3 1
378#define CONFIG_TSEC3_NAME "eTSEC3"
379
380#define CONFIG_PIXIS_SGMII_CMD
381#define CONFIG_FSL_SGMII_RISER 1
382#define SGMII_RISER_PHY_OFFSET 0x1c
383
384#define TSEC1_PHY_ADDR 0
385#define TSEC3_PHY_ADDR 1
386
387#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
388#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
389
390#define TSEC1_PHYIDX 0
391#define TSEC3_PHYIDX 0
392
393#define CONFIG_ETHPRIME "eTSEC1"
394
395#define CONFIG_PHY_GIGE 1
396#endif
397
398
399
400
401#define CONFIG_ENV_IS_IN_FLASH 1
402#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
403#define CONFIG_ENV_ADDR 0xfff80000
404#else
405#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
406#endif
407#define CONFIG_ENV_SIZE 0x2000
408#define CONFIG_ENV_SECT_SIZE 0x10000
409
410#define CONFIG_LOADS_ECHO 1
411#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
412
413
414
415
416#define CONFIG_BOOTP_BOOTFILESIZE
417#define CONFIG_BOOTP_BOOTPATH
418#define CONFIG_BOOTP_GATEWAY
419#define CONFIG_BOOTP_HOSTNAME
420
421
422
423
424
425#include <config_cmd_default.h>
426
427#define CONFIG_CMD_PING
428#define CONFIG_CMD_I2C
429#define CONFIG_CMD_MII
430#define CONFIG_CMD_ELF
431#define CONFIG_CMD_IRQ
432#define CONFIG_CMD_SETEXPR
433
434#if defined(CONFIG_PCI)
435 #define CONFIG_CMD_PCI
436 #define CONFIG_CMD_NET
437 #define CONFIG_CMD_SCSI
438 #define CONFIG_CMD_EXT2
439#endif
440
441
442#undef CONFIG_WATCHDOG
443
444
445
446
447#define CONFIG_SYS_LONGHELP
448#define CONFIG_CMDLINE_EDITING
449#define CONFIG_SYS_LOAD_ADDR 0x2000000
450#define CONFIG_SYS_PROMPT "=> "
451#if defined(CONFIG_CMD_KGDB)
452#define CONFIG_SYS_CBSIZE 1024
453#else
454#define CONFIG_SYS_CBSIZE 256
455#endif
456#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
457#define CONFIG_SYS_MAXARGS 16
458#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
459#define CONFIG_SYS_HZ 1000
460
461
462
463
464
465
466#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
467
468
469
470
471
472
473#define BOOTFLAG_COLD 0x01
474#define BOOTFLAG_WARM 0x02
475
476#if defined(CONFIG_CMD_KGDB)
477#define CONFIG_KGDB_BAUDRATE 230400
478#define CONFIG_KGDB_SER_INDEX 2
479#endif
480
481
482
483
484
485
486#if defined(CONFIG_TSEC_ENET)
487#define CONFIG_HAS_ETH0
488#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
489#define CONFIG_HAS_ETH1
490#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
491#endif
492
493#define CONFIG_IPADDR 192.168.1.251
494
495#define CONFIG_HOSTNAME 8544ds_unknown
496#define CONFIG_ROOTPATH /nfs/mpc85xx
497#define CONFIG_BOOTFILE 8544ds/uImage.uboot
498#define CONFIG_UBOOTPATH 8544ds/u-boot.bin
499
500#define CONFIG_SERVERIP 192.168.1.1
501#define CONFIG_GATEWAYIP 192.168.1.1
502#define CONFIG_NETMASK 255.255.0.0
503
504#define CONFIG_LOADADDR 1000000
505
506#define CONFIG_BOOTDELAY 10
507#undef CONFIG_BOOTARGS
508
509#define CONFIG_BAUDRATE 115200
510
511#define CONFIG_EXTRA_ENV_SETTINGS \
512 "netdev=eth0\0" \
513 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
514 "tftpflash=tftpboot $loadaddr $uboot; " \
515 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
516 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
517 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
518 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
519 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
520 "consoledev=ttyS0\0" \
521 "ramdiskaddr=2000000\0" \
522 "ramdiskfile=8544ds/ramdisk.uboot\0" \
523 "fdtaddr=c00000\0" \
524 "fdtfile=8544ds/mpc8544ds.dtb\0" \
525 "bdev=sda3\0"
526
527#define CONFIG_NFSBOOTCOMMAND \
528 "setenv bootargs root=/dev/nfs rw " \
529 "nfsroot=$serverip:$rootpath " \
530 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
531 "console=$consoledev,$baudrate $othbootargs;" \
532 "tftp $loadaddr $bootfile;" \
533 "tftp $fdtaddr $fdtfile;" \
534 "bootm $loadaddr - $fdtaddr"
535
536#define CONFIG_RAMBOOTCOMMAND \
537 "setenv bootargs root=/dev/ram rw " \
538 "console=$consoledev,$baudrate $othbootargs;" \
539 "tftp $ramdiskaddr $ramdiskfile;" \
540 "tftp $loadaddr $bootfile;" \
541 "tftp $fdtaddr $fdtfile;" \
542 "bootm $loadaddr $ramdiskaddr $fdtaddr"
543
544#define CONFIG_BOOTCOMMAND \
545 "setenv bootargs root=/dev/$bdev rw " \
546 "console=$consoledev,$baudrate $othbootargs;" \
547 "tftp $loadaddr $bootfile;" \
548 "tftp $fdtaddr $fdtfile;" \
549 "bootm $loadaddr - $fdtaddr"
550
551#endif
552