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26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30
31#define CONFIG_BOOKE 1
32#define CONFIG_E500 1
33#define CONFIG_MPC85xx 1
34#define CONFIG_P2020 1
35#define CONFIG_P2020DS 1
36#define CONFIG_MP 1
37#define CONFIG_NUM_CPUS 2
38
39#define CONFIG_FSL_ELBC 1
40#define CONFIG_PCI 1
41#define CONFIG_PCIE1 1
42#define CONFIG_PCIE2 1
43#define CONFIG_PCIE3 1
44#define CONFIG_FSL_PCI_INIT 1
45#define CONFIG_FSL_PCIE_RESET 1
46#define CONFIG_SYS_PCI_64BIT 1
47
48#define CONFIG_FSL_LAW 1
49#define CONFIG_E1000 1
50
51#define CONFIG_TSEC_ENET
52#define CONFIG_ENV_OVERWRITE
53
54
55
56
57
58
59#define CONFIG_ASSUME_AMD_FLASH
60
61#ifndef __ASSEMBLY__
62extern unsigned long calculate_board_sys_clk(unsigned long dummy);
63extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
64
65
66#endif
67#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0)
68#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0)
69#define CONFIG_ICS307_REFCLK_HZ 33333000
70#define CONFIG_GET_CLK_FROM_ICS307
71
72
73
74
75
76#define CONFIG_L2_CACHE
77#define CONFIG_BTB
78
79#define CONFIG_ENABLE_36BIT_PHYS 1
80
81#ifdef CONFIG_PHYS_64BIT
82#define CONFIG_ADDR_MAP 1
83#define CONFIG_SYS_NUM_ADDR_MAP 16
84#endif
85
86#define CONFIG_SYS_MEMTEST_START 0x00000000
87#define CONFIG_SYS_MEMTEST_END 0x7fffffff
88#define CONFIG_PANIC_HANG
89
90
91
92
93
94#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
95#define CONFIG_SYS_CCSRBAR 0xffe00000
96#ifdef CONFIG_PHYS_64BIT
97#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
98#else
99#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
100#endif
101#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
102
103#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
104#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
105#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
106
107
108#define CONFIG_SYS_DDR_TLB_START 9
109#define CONFIG_VERY_BIG_RAM
110#define CONFIG_FSL_DDR3 1
111#undef CONFIG_FSL_DDR_INTERACTIVE
112
113
114
115
116#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
117#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
118
119#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
120#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
121
122#define CONFIG_NUM_DDR_CONTROLLERS 1
123#define CONFIG_DIMM_SLOTS_PER_CTLR 1
124#define CONFIG_CHIP_SELECTS_PER_CTRL 2
125
126
127#define CONFIG_SYS_SPD_BUS_NUM 0
128#define SPD_EEPROM_ADDRESS1 0x51
129
130
131#define CONFIG_SYS_SDRAM_SIZE 1024
132
133
134#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
135#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
136#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
137#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
138#define CONFIG_SYS_DDR_TIMING_3 0x00020000
139#define CONFIG_SYS_DDR_TIMING_0 0x00330804
140#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
141#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
142#define CONFIG_SYS_DDR_MODE_1 0x00421422
143#define CONFIG_SYS_DDR_MODE_2 0x00000000
144#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
145#define CONFIG_SYS_DDR_INTERVAL 0x61800100
146#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
147#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
148#define CONFIG_SYS_DDR_TIMING_4 0x00220001
149#define CONFIG_SYS_DDR_TIMING_5 0x03402400
150#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
151#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
152#define CONFIG_SYS_DDR_CONTROL 0xE7000000
153#define CONFIG_SYS_DDR_CONTROL2 0x24400011
154#define CONFIG_SYS_DDR_CDR1 0x00040000
155#define CONFIG_SYS_DDR_CDR2 0x00000000
156
157#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
158#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
159#define CONFIG_SYS_DDR_SBE 0x00010000
160
161
162#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F
163#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000
164#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
165#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
166#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
167#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000
168
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187
188
189#undef CONFIG_CLOCKS_IN_MHZ
190
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214#define CONFIG_SYS_FLASH_BASE 0xe0000000
215#ifdef CONFIG_PHYS_64BIT
216#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
217#else
218#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
219#endif
220
221#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
222#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
223
224#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
225#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
226
227#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
228#define CONFIG_SYS_FLASH_QUIET_TEST
229#define CONFIG_FLASH_SHOW_PROGRESS 45
230
231#define CONFIG_SYS_MAX_FLASH_BANKS 2
232#define CONFIG_SYS_MAX_FLASH_SECT 1024
233#undef CONFIG_SYS_FLASH_CHECKSUM
234#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
235#define CONFIG_SYS_FLASH_WRITE_TOUT 500
236
237#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
238
239#define CONFIG_FLASH_CFI_DRIVER
240#define CONFIG_SYS_FLASH_CFI
241#define CONFIG_SYS_FLASH_EMPTY_INFO
242#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
243
244#define CONFIG_BOARD_EARLY_INIT_R
245
246#define CONFIG_FSL_PIXIS 1
247#define PIXIS_BASE 0xffdf0000
248#ifdef CONFIG_PHYS_64BIT
249#define PIXIS_BASE_PHYS 0xfffdf0000ull
250#else
251#define PIXIS_BASE_PHYS PIXIS_BASE
252#endif
253
254#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
255#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
256
257#define PIXIS_ID 0x0
258#define PIXIS_VER 0x1
259#define PIXIS_PVER 0x2
260#define PIXIS_CSR 0x3
261#define PIXIS_RST 0x4
262#define PIXIS_PWR 0x5
263#define PIXIS_AUX 0x6
264#define PIXIS_SPD 0x7
265#define PIXIS_AUX2 0x8
266#define PIXIS_VCTL 0x10
267#define PIXIS_VSTAT 0x11
268#define PIXIS_VCFGEN0 0x12
269#define PIXIS_VCFGEN1 0x13
270#define PIXIS_VCORE0 0x14
271#define PIXIS_VBOOT 0x16
272#define PIXIS_VSPEED0 0x17
273#define PIXIS_VSPEED1 0x18
274#define PIXIS_VSPEED2 0x19
275#define PIXIS_VSYSCLK0 0x19
276#define PIXIS_VSYSCLK1 0x1A
277#define PIXIS_VSYSCLK2 0x1B
278#define PIXIS_VDDRCLK0 0x1C
279#define PIXIS_VDDRCLK1 0x1D
280#define PIXIS_VDDRCLK2 0x1E
281
282#define PIXIS_VWATCH 0x24
283#define PIXIS_LED 0x25
284
285#define PIXIS_SW(x) 0x20 + (x - 1) * 2
286#define PIXIS_EN(x) 0x21 + (x - 1) * 2
287#define PIXIS_SW7_LBMAP 0xc0
288#define PIXIS_SW7_VBANK 0x30
289
290
291#define PIXIS_VCLKH 0x19
292#define PIXIS_VCLKL 0x1A
293#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
294#define PIXIS_VSPEED2_TSEC1SER 0x8
295#define PIXIS_VSPEED2_TSEC2SER 0x4
296#define PIXIS_VSPEED2_TSEC3SER 0x2
297#define PIXIS_VSPEED2_TSEC4SER 0x1
298#define PIXIS_VCFGEN1_TSEC1SER 0x20
299#define PIXIS_VCFGEN1_TSEC2SER 0x20
300#define PIXIS_VCFGEN1_TSEC3SER 0x20
301#define PIXIS_VCFGEN1_TSEC4SER 0x20
302#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
303 | PIXIS_VSPEED2_TSEC2SER \
304 | PIXIS_VSPEED2_TSEC3SER \
305 | PIXIS_VSPEED2_TSEC4SER)
306#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
307 | PIXIS_VCFGEN1_TSEC2SER \
308 | PIXIS_VCFGEN1_TSEC3SER \
309 | PIXIS_VCFGEN1_TSEC4SER)
310
311#define CONFIG_SYS_INIT_RAM_LOCK 1
312#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
313#define CONFIG_SYS_INIT_RAM_END 0x00004000
314
315#define CONFIG_SYS_GBL_DATA_SIZE 128
316#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
317#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
318
319#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
320#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
321
322#define CONFIG_SYS_NAND_BASE 0xffa00000
323#ifdef CONFIG_PHYS_64BIT
324#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
325#else
326#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
327#endif
328#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
329 CONFIG_SYS_NAND_BASE + 0x40000, \
330 CONFIG_SYS_NAND_BASE + 0x80000,\
331 CONFIG_SYS_NAND_BASE + 0xC0000}
332#define CONFIG_SYS_MAX_NAND_DEVICE 4
333#define CONFIG_MTD_NAND_VERIFY_WRITE
334#define CONFIG_CMD_NAND 1
335#define CONFIG_NAND_FSL_ELBC 1
336#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
337
338
339#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
340 | (2<<BR_DECC_SHIFT) \
341 | BR_PS_8 \
342 | BR_MS_FCM \
343 | BR_V)
344#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 \
345 | OR_FCM_PGS \
346 | OR_FCM_CSCT \
347 | OR_FCM_CST \
348 | OR_FCM_CHT \
349 | OR_FCM_SCY_1 \
350 | OR_FCM_TRLX \
351 | OR_FCM_EHTR)
352
353#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
354#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
355#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM
356#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM
357
358#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
359 | (2<<BR_DECC_SHIFT) \
360 | BR_PS_8 \
361 | BR_MS_FCM \
362 | BR_V)
363#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM
364#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
365 | (2<<BR_DECC_SHIFT) \
366 | BR_PS_8 \
367 | BR_MS_FCM \
368 | BR_V)
369#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM
370
371#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
372 | (2<<BR_DECC_SHIFT) \
373 | BR_PS_8 \
374 | BR_MS_FCM \
375 | BR_V)
376#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM
377
378
379
380
381
382#define CONFIG_CONS_INDEX 1
383#undef CONFIG_SERIAL_SOFTWARE_FIFO
384#define CONFIG_SYS_NS16550
385#define CONFIG_SYS_NS16550_SERIAL
386#define CONFIG_SYS_NS16550_REG_SIZE 1
387#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
388
389#define CONFIG_SYS_BAUDRATE_TABLE \
390 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
391
392#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
393#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
394
395
396#define CONFIG_SYS_HUSH_PARSER
397#ifdef CONFIG_SYS_HUSH_PARSER
398#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
399#endif
400
401
402
403
404#define CONFIG_OF_LIBFDT 1
405#define CONFIG_OF_BOARD_SETUP 1
406#define CONFIG_OF_STDOUT_VIA_ALIAS 1
407
408#define CONFIG_SYS_64BIT_VSPRINTF 1
409#define CONFIG_SYS_64BIT_STRTOUL 1
410
411
412#define CONFIG_FIT 1
413#define CONFIG_FIT_VERBOSE 1
414
415
416#define CONFIG_FSL_I2C
417#define CONFIG_HARD_I2C
418#undef CONFIG_SOFT_I2C
419#define CONFIG_I2C_MULTI_BUS
420#define CONFIG_SYS_I2C_SPEED 400000
421#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
422#define CONFIG_SYS_I2C_SLAVE 0x7F
423#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}
424#define CONFIG_SYS_I2C_OFFSET 0x3000
425#define CONFIG_SYS_I2C2_OFFSET 0x3100
426
427
428
429
430#define CONFIG_ID_EEPROM
431#ifdef CONFIG_ID_EEPROM
432#define CONFIG_SYS_I2C_EEPROM_NXID
433#endif
434#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
435#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
436#define CONFIG_SYS_EEPROM_BUS_NUM 0
437
438
439
440
441
442
443
444#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
445#ifdef CONFIG_PHYS_64BIT
446#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
447#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
448#else
449#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
450#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
451#endif
452#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
453#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
454#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
455#ifdef CONFIG_PHYS_64BIT
456#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
457#else
458#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
459#endif
460#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
461
462
463#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
464#ifdef CONFIG_PHYS_64BIT
465#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
466#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
467#else
468#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
469#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
470#endif
471#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
472#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
473#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
474#ifdef CONFIG_PHYS_64BIT
475#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
476#else
477#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
478#endif
479#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
480
481
482#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
483#ifdef CONFIG_PHYS_64BIT
484#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
485#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
486#else
487#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
488#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
489#endif
490#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
491#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
492#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
493#ifdef CONFIG_PHYS_64BIT
494#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
495#else
496#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
497#endif
498#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
499
500#if defined(CONFIG_PCI)
501
502
503#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
504
505
506#define CONFIG_VIDEO
507
508#if defined(CONFIG_VIDEO)
509#define CONFIG_BIOSEMU
510#define CONFIG_CFB_CONSOLE
511#define CONFIG_VIDEO_SW_CURSOR
512#define CONFIG_VGA_AS_SINGLE_DEVICE
513#define CONFIG_ATI_RADEON_FB
514#define CONFIG_VIDEO_LOGO
515
516#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
517#endif
518
519#define CONFIG_NET_MULTI
520#define CONFIG_PCI_PNP
521
522#undef CONFIG_EEPRO100
523#undef CONFIG_TULIP
524#define CONFIG_RTL8139
525
526#ifndef CONFIG_PCI_PNP
527 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
528 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
529 #define PCI_IDSEL_NUMBER 0x11
530#endif
531
532#define CONFIG_PCI_SCAN_SHOW
533#define CONFIG_DOS_PARTITION
534#define CONFIG_SCSI_AHCI
535
536#ifdef CONFIG_SCSI_AHCI
537#define CONFIG_SATA_ULI5288
538#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
539#define CONFIG_SYS_SCSI_MAX_LUN 1
540#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
541#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
542#endif
543
544#endif
545
546
547#if defined(CONFIG_TSEC_ENET)
548
549#ifndef CONFIG_NET_MULTI
550#define CONFIG_NET_MULTI 1
551#endif
552
553#define CONFIG_MII 1
554#define CONFIG_MII_DEFAULT_TSEC 1
555#define CONFIG_TSEC1 1
556#define CONFIG_TSEC1_NAME "eTSEC1"
557#define CONFIG_TSEC2 1
558#define CONFIG_TSEC2_NAME "eTSEC2"
559#define CONFIG_TSEC3 1
560#define CONFIG_TSEC3_NAME "eTSEC3"
561
562#define CONFIG_PIXIS_SGMII_CMD
563#define CONFIG_FSL_SGMII_RISER 1
564#define SGMII_RISER_PHY_OFFSET 0x1b
565
566#ifdef CONFIG_FSL_SGMII_RISER
567#define CONFIG_SYS_TBIPA_VALUE 0x10
568#endif
569
570#define TSEC1_PHY_ADDR 0
571#define TSEC2_PHY_ADDR 1
572#define TSEC3_PHY_ADDR 2
573
574#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
575#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
576#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
577
578#define TSEC1_PHYIDX 0
579#define TSEC2_PHYIDX 0
580#define TSEC3_PHYIDX 0
581
582#define CONFIG_ETHPRIME "eTSEC1"
583
584#define CONFIG_PHY_GIGE 1
585#endif
586
587
588
589
590#define CONFIG_ENV_IS_IN_FLASH 1
591#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
592#define CONFIG_ENV_ADDR 0xfff80000
593#else
594#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
595#endif
596#define CONFIG_ENV_SIZE 0x2000
597#define CONFIG_ENV_SECT_SIZE 0x20000
598
599#define CONFIG_LOADS_ECHO 1
600#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
601
602
603
604
605#include <config_cmd_default.h>
606
607#define CONFIG_CMD_IRQ
608#define CONFIG_CMD_PING
609#define CONFIG_CMD_I2C
610#define CONFIG_CMD_MII
611#define CONFIG_CMD_ELF
612#define CONFIG_CMD_IRQ
613#define CONFIG_CMD_SETEXPR
614
615#if defined(CONFIG_PCI)
616#define CONFIG_CMD_PCI
617#define CONFIG_CMD_NET
618#define CONFIG_CMD_SCSI
619#define CONFIG_CMD_EXT2
620#endif
621
622#undef CONFIG_WATCHDOG
623
624
625
626
627#define CONFIG_SYS_LONGHELP
628#define CONFIG_CMDLINE_EDITING
629#define CONFIG_SYS_LOAD_ADDR 0x2000000
630#define CONFIG_SYS_PROMPT "=> "
631#if defined(CONFIG_CMD_KGDB)
632#define CONFIG_SYS_CBSIZE 1024
633#else
634#define CONFIG_SYS_CBSIZE 256
635#endif
636#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
637#define CONFIG_SYS_MAXARGS 16
638#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
639#define CONFIG_SYS_HZ 1000
640
641
642
643
644
645
646#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
647
648
649
650
651
652
653#define BOOTFLAG_COLD 0x01
654#define BOOTFLAG_WARM 0x02
655
656#if defined(CONFIG_CMD_KGDB)
657#define CONFIG_KGDB_BAUDRATE 230400
658#define CONFIG_KGDB_SER_INDEX 2
659#endif
660
661
662
663
664
665
666#if defined(CONFIG_TSEC_ENET)
667#define CONFIG_HAS_ETH0
668#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
669#define CONFIG_HAS_ETH1
670#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
671#define CONFIG_HAS_ETH2
672#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
673#define CONFIG_HAS_ETH3
674#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
675#endif
676
677#define CONFIG_IPADDR 192.168.1.254
678
679#define CONFIG_HOSTNAME unknown
680#define CONFIG_ROOTPATH /opt/nfsroot
681#define CONFIG_BOOTFILE uImage
682#define CONFIG_UBOOTPATH u-boot.bin
683
684#define CONFIG_SERVERIP 192.168.1.1
685#define CONFIG_GATEWAYIP 192.168.1.1
686#define CONFIG_NETMASK 255.255.255.0
687
688
689#define CONFIG_LOADADDR 1000000
690
691#define CONFIG_BOOTDELAY 10
692#undef CONFIG_BOOTARGS
693
694#define CONFIG_BAUDRATE 115200
695
696#define CONFIG_EXTRA_ENV_SETTINGS \
697 "perf_mode=stable\0" \
698 "memctl_intlv_ctl=2\0" \
699 "netdev=eth0\0" \
700 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
701 "tftpflash=tftpboot $loadaddr $uboot; " \
702 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
703 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
704 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
705 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
706 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
707 "consoledev=ttyS0\0" \
708 "ramdiskaddr=2000000\0" \
709 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
710 "fdtaddr=c00000\0" \
711 "fdtfile=p2020ds/p2020ds.dtb\0" \
712 "bdev=sda3\0"
713
714#define CONFIG_HDBOOT \
715 "setenv bootargs root=/dev/$bdev rw " \
716 "console=$consoledev,$baudrate $othbootargs;" \
717 "tftp $loadaddr $bootfile;" \
718 "tftp $fdtaddr $fdtfile;" \
719 "bootm $loadaddr - $fdtaddr"
720
721#define CONFIG_NFSBOOTCOMMAND \
722 "setenv bootargs root=/dev/nfs rw " \
723 "nfsroot=$serverip:$rootpath " \
724 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
725 "console=$consoledev,$baudrate $othbootargs;" \
726 "tftp $loadaddr $bootfile;" \
727 "tftp $fdtaddr $fdtfile;" \
728 "bootm $loadaddr - $fdtaddr"
729
730#define CONFIG_RAMBOOTCOMMAND \
731 "setenv bootargs root=/dev/ram rw " \
732 "console=$consoledev,$baudrate $othbootargs;" \
733 "tftp $ramdiskaddr $ramdiskfile;" \
734 "tftp $loadaddr $bootfile;" \
735 "tftp $fdtaddr $fdtfile;" \
736 "bootm $loadaddr $ramdiskaddr $fdtaddr"
737
738#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
739
740#endif
741