1/* 2 * (C) Copyright 2000, 2001, 2002 3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. 4 * 5 * Configuration for the Auerswald Innokom CPU board. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * include/configs/innokom.h - configuration options, board specific 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ 38#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ 39 40#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 41 /* for timer/console/ethernet */ 42 43/* we will never enable dcache, because we have to setup MMU first */ 44#define CONFIG_SYS_NO_DCACHE 45 46/* 47 * Hardware drivers 48 */ 49 50/* 51 * select serial console configuration 52 */ 53#define CONFIG_PXA_SERIAL 54#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ 55 56/* allow to overwrite serial and ethaddr */ 57#define CONFIG_ENV_OVERWRITE 58 59#define CONFIG_BAUDRATE 19200 60#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ 61 62 63/* 64 * BOOTP options 65 */ 66#define CONFIG_BOOTP_BOOTFILESIZE 67#define CONFIG_BOOTP_BOOTPATH 68#define CONFIG_BOOTP_GATEWAY 69#define CONFIG_BOOTP_HOSTNAME 70 71 72/* 73 * Command line configuration. 74 */ 75 76#define CONFIG_CMD_ASKENV 77#define CONFIG_CMD_BDI 78#define CONFIG_CMD_CACHE 79#define CONFIG_CMD_DHCP 80#define CONFIG_CMD_ECHO 81#define CONFIG_CMD_SAVEENV 82#define CONFIG_CMD_FLASH 83#define CONFIG_CMD_I2C 84#define CONFIG_CMD_IMI 85#define CONFIG_CMD_LOADB 86#define CONFIG_CMD_MEMORY 87#define CONFIG_CMD_NET 88#define CONFIG_CMD_RUN 89 90 91#define CONFIG_BOOTDELAY 3 92/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ 93#define CONFIG_BOOTARGS "console=ttyS0,19200" 94#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF 95#define CONFIG_NETMASK 255.255.255.0 96#define CONFIG_IPADDR 192.168.1.56 97#define CONFIG_SERVERIP 192.168.1.2 98#define CONFIG_BOOTCOMMAND "bootm 0x40000" 99#define CONFIG_SHOW_BOOT_PROGRESS 100 101#define CONFIG_CMDLINE_TAG 1 102 103/* 104 * Miscellaneous configurable options 105 */ 106 107/* 108 * Size of malloc() pool 109 */ 110#define CONFIG_SYS_MALLOC_LEN (256*1024) 111#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 112 113#define CONFIG_SYS_LONGHELP /* undef to save memory */ 114#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ 115#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 116#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 118#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 119 120#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 121#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 122 123#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */ 124 125#define CONFIG_SYS_HZ 1000 126 /* RS: the oscillator is actually 3680130?? */ 127 128#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ 129 /* 0101000001 */ 130 /* ^^^^^ Memory Speed 99.53 MHz */ 131 /* ^^ Run Mode Speed = 2x Mem Speed */ 132 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ 133 134#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ 135 136 /* valid baudrates */ 137#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 138 139/* 140 * I2C bus 141 */ 142#define CONFIG_HARD_I2C 1 143#define CONFIG_SYS_I2C_SPEED 50000 144#define CONFIG_SYS_I2C_SLAVE 0xfe 145 146#define CONFIG_ENV_IS_IN_EEPROM 1 147 148#define CONFIG_ENV_OFFSET 0x00 /* environment starts here */ 149#define CONFIG_ENV_SIZE 1024 /* 1 KiB */ 150#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */ 151#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ 152#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */ 153#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* length of address */ 154#define CONFIG_SYS_EEPROM_SIZE 4096 /* size in bytes */ 155#define CONFIG_SYS_I2C_INIT_BOARD 1 /* board has it's own init */ 156 157/* 158 * SMSC91C111 Network Card 159 */ 160#define CONFIG_DRIVER_SMC91111 1 161#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */ 162#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ 163#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ 164#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */ 165#undef CONFIG_SHOW_ACTIVITY 166#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ 167 168/* 169 * Stack sizes 170 * 171 * The stack sizes are set up in start.S using the settings below 172 */ 173#define CONFIG_STACKSIZE (128*1024) /* regular stack */ 174#ifdef CONFIG_USE_IRQ 175#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 176#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 177#endif 178 179/* 180 * Physical Memory Map 181 */ 182#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 183#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 184#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 185 186#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 187#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ 188 189#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */ 190#define CONFIG_SYS_DRAM_SIZE 0x04000000 191 192#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 193 194/* 195 * JFFS2 partitions 196 * 197 */ 198/* development flash */ 199#define CONFIG_MTD_INNOKOM_16MB 1 200#undef CONFIG_MTD_INNOKOM_64MB 201 202/* production flash */ 203/* 204#define CONFIG_MTD_INNOKOM_64MB 1 205#undef CONFIG_MTD_INNOKOM_16MB 206*/ 207 208/* No command line, one static partition, whole device */ 209#undef CONFIG_CMD_MTDPARTS 210#define CONFIG_JFFS2_DEV "nor0" 211#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 212#define CONFIG_JFFS2_PART_OFFSET 0x00000000 213 214/* mtdparts command line support */ 215/* Note: fake mtd_id used, no linux mtd map file */ 216/* 217#define CONFIG_CMD_MTDPARTS 218#define MTDIDS_DEFAULT "nor0=innokom-0" 219*/ 220 221/* development flash */ 222/* 223#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)" 224*/ 225 226/* production flash */ 227/* 228#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)" 229*/ 230 231/* 232 * GPIO settings 233 * 234 * GP15 == nCS1 is 1 235 * GP24 == SFRM is 1 236 * GP25 == TXD is 1 237 * GP33 == nCS5 is 1 238 * GP39 == FFTXD is 1 239 * GP41 == RTS is 1 240 * GP47 == TXD is 1 241 * GP49 == nPWE is 1 242 * GP62 == LED_B is 1 243 * GP63 == TDM_OE is 1 244 * GP78 == nCS2 is 1 245 * GP79 == nCS3 is 1 246 * GP80 == nCS4 is 1 247 */ 248#define CONFIG_SYS_GPSR0_VAL 0x03008000 249#define CONFIG_SYS_GPSR1_VAL 0xC0028282 250#define CONFIG_SYS_GPSR2_VAL 0x0001C000 251 252/* GP02 == DON_RST is 0 253 * GP23 == SCLK is 0 254 * GP45 == USB_ACT is 0 255 * GP60 == PLLEN is 0 256 * GP61 == LED_A is 0 257 * GP73 == SWUPD_LED is 0 258 */ 259#define CONFIG_SYS_GPCR0_VAL 0x00800004 260#define CONFIG_SYS_GPCR1_VAL 0x30002000 261#define CONFIG_SYS_GPCR2_VAL 0x00000100 262 263/* GP00 == DON_READY is input 264 * GP01 == DON_OK is input 265 * GP02 == DON_RST is output 266 * GP03 == RESET_IND is input 267 * GP07 == RES11 is input 268 * GP09 == RES12 is input 269 * GP11 == SWUPDATE is input 270 * GP14 == nPOWEROK is input 271 * GP15 == nCS1 is output 272 * GP17 == RES22 is input 273 * GP18 == RDY is input 274 * GP23 == SCLK is output 275 * GP24 == SFRM is output 276 * GP25 == TXD is output 277 * GP26 == RXD is input 278 * GP32 == RES21 is input 279 * GP33 == nCS5 is output 280 * GP34 == FFRXD is input 281 * GP35 == CTS is input 282 * GP39 == FFTXD is output 283 * GP41 == RTS is output 284 * GP42 == USB_OK is input 285 * GP45 == USB_ACT is output 286 * GP46 == RXD is input 287 * GP47 == TXD is output 288 * GP49 == nPWE is output 289 * GP58 == nCPUBUSINT is input 290 * GP59 == LANINT is input 291 * GP60 == PLLEN is output 292 * GP61 == LED_A is output 293 * GP62 == LED_B is output 294 * GP63 == TDM_OE is output 295 * GP64 == nDSPINT is input 296 * GP65 == STRAP0 is input 297 * GP67 == STRAP1 is input 298 * GP69 == STRAP2 is input 299 * GP70 == STRAP3 is input 300 * GP71 == STRAP4 is input 301 * GP73 == SWUPD_LED is output 302 * GP78 == nCS2 is output 303 * GP79 == nCS3 is output 304 * GP80 == nCS4 is output 305 */ 306#define CONFIG_SYS_GPDR0_VAL 0x03808004 307#define CONFIG_SYS_GPDR1_VAL 0xF002A282 308#define CONFIG_SYS_GPDR2_VAL 0x0001C200 309 310/* GP15 == nCS1 is AF10 311 * GP18 == RDY is AF01 312 * GP23 == SCLK is AF10 313 * GP24 == SFRM is AF10 314 * GP25 == TXD is AF10 315 * GP26 == RXD is AF01 316 * GP33 == nCS5 is AF10 317 * GP34 == FFRXD is AF01 318 * GP35 == CTS is AF01 319 * GP39 == FFTXD is AF10 320 * GP41 == RTS is AF10 321 * GP46 == RXD is AF10 322 * GP47 == TXD is AF01 323 * GP49 == nPWE is AF10 324 * GP78 == nCS2 is AF10 325 * GP79 == nCS3 is AF10 326 * GP80 == nCS4 is AF10 327 */ 328#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 329#define CONFIG_SYS_GAFR0_U_VAL 0x001A8010 330#define CONFIG_SYS_GAFR1_L_VAL 0x60088058 331#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 332#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 333#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 334 335 336/* FIXME: set GPIO_RER/FER */ 337 338/* RDH = 1 339 * PH = 1 340 * VFS = 1 341 * BFS = 1 342 * SSS = 1 343 */ 344#define CONFIG_SYS_PSSR_VAL 0x37 345 346/* 347 * Memory settings 348 * 349 * This is the configuration for nCS0/1 -> flash banks 350 * configuration for nCS1: 351 * [31] 0 - Slower Device 352 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns 353 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns 354 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns 355 * [19] 1 - 16 Bit bus width 356 * [18:16] 000 - nonburst RAM or FLASH 357 * configuration for nCS0: 358 * [15] 0 - Slower Device 359 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns 360 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns 361 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns 362 * [03] 1 - 16 Bit bus width 363 * [02:00] 000 - nonburst RAM or FLASH 364 */ 365#define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */ 366 367/* This is the configuration for nCS2/3 -> TDM-Switch, DSP 368 * configuration for nCS3: DSP 369 * [31] 0 - Slower Device 370 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns 371 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns 372 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns 373 * [19] 1 - 16 Bit bus width 374 * [18:16] 100 - variable latency I/O 375 * configuration for nCS2: TDM-Switch 376 * [15] 0 - Slower Device 377 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns 378 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns 379 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns 380 * [03] 1 - 16 Bit bus width 381 * [02:00] 100 - variable latency I/O 382 */ 383#define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */ 384 385/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller 386 * 387 * configuration for nCS5: LAN Controller 388 * [31] 0 - Slower Device 389 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns 390 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns 391 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns 392 * [19] 1 - 16 Bit bus width 393 * [18:16] 100 - variable latency I/O 394 * configuration for nCS4: ExtBus 395 * [15] 0 - Slower Device 396 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns 397 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns 398 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns 399 * [03] 1 - 16 Bit bus width 400 * [02:00] 100 - variable latency I/O 401 */ 402#define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ 403 404/* MDCNFG: SDRAM Configuration Register 405 * 406 * [31:29] 000 - reserved 407 * [28] 0 - no SA1111 compatiblity mode 408 * [27] 0 - latch return data with return clock 409 * [26] 0 - alternate addressing for pair 2/3 410 * [25:24] 00 - timings 411 * [23] 0 - internal banks in lower partition 2/3 (not used) 412 * [22:21] 00 - row address bits for partition 2/3 (not used) 413 * [20:19] 00 - column address bits for partition 2/3 (not used) 414 * [18] 0 - SDRAM partition 2/3 width is 32 bit 415 * [17] 0 - SDRAM partition 3 disabled 416 * [16] 0 - SDRAM partition 2 disabled 417 * [15:13] 000 - reserved 418 * [12] 1 - SA1111 compatiblity mode 419 * [11] 1 - latch return data with return clock 420 * [10] 0 - no alternate addressing for pair 0/1 421 * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk 422 * [7] 1 - 4 internal banks in lower partition pair 423 * [06:05] 10 - 13 row address bits for partition 0/1 424 * [04:03] 01 - 9 column address bits for partition 0/1 425 * [02] 0 - SDRAM partition 0/1 width is 32 bit 426 * [01] 0 - disable SDRAM partition 1 427 * [00] 1 - enable SDRAM partition 0 428 */ 429/* use the configuration above but disable partition 0 */ 430#define CONFIG_SYS_MDCNFG_VAL 0x000019c8 431 432/* MDREFR: SDRAM Refresh Control Register 433 * 434 * [32:26] 0 - reserved 435 * [25] 0 - K2FREE: not free running 436 * [24] 0 - K1FREE: not free running 437 * [23] 1 - K0FREE: not free running 438 * [22] 0 - SLFRSH: self refresh disabled 439 * [21] 0 - reserved 440 * [20] 0 - APD: no auto power down 441 * [19] 0 - K2DB2: SDCLK2 is MemClk 442 * [18] 0 - K2RUN: disable SDCLK2 443 * [17] 0 - K1DB2: SDCLK1 is MemClk 444 * [16] 1 - K1RUN: enable SDCLK1 445 * [15] 1 - E1PIN: SDRAM clock enable 446 * [14] 1 - K0DB2: SDCLK0 is MemClk 447 * [13] 0 - K0RUN: disable SDCLK0 448 * [12] 1 - E0PIN: disable SDCKE0 449 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 450 */ 451#define CONFIG_SYS_MDREFR_VAL 0x0081D018 452 453/* MDMRS: Mode Register Set Configuration Register 454 * 455 * [31] 0 - reserved 456 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) 457 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) 458 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) 459 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) 460 * [15] 0 - reserved 461 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. 462 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. 463 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. 464 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. 465 */ 466#define CONFIG_SYS_MDMRS_VAL 0x00020022 467 468/* 469 * PCMCIA and CF Interfaces 470 */ 471#define CONFIG_SYS_MECR_VAL 0x00000000 472#define CONFIG_SYS_MCMEM0_VAL 0x00000000 473#define CONFIG_SYS_MCMEM1_VAL 0x00000000 474#define CONFIG_SYS_MCATT0_VAL 0x00000000 475#define CONFIG_SYS_MCATT1_VAL 0x00000000 476#define CONFIG_SYS_MCIO0_VAL 0x00000000 477#define CONFIG_SYS_MCIO1_VAL 0x00000000 478 479/* 480#define CSB226_USER_LED0 0x00000008 481#define CSB226_USER_LED1 0x00000010 482#define CSB226_USER_LED2 0x00000020 483*/ 484 485/* 486 * FLASH and environment organization 487 */ 488#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 489#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ 490 491/* timeout values are in ticks */ 492#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 493#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 494 495#endif /* __CONFIG_H */ 496