LXR uboot/include/configs/kmeter1.h

   1/*
   2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3 *                    Dave Liu <daveliu@freescale.com>
   4 *
   5 * Copyright (C) 2007 Logic Product Development, Inc.
   6 *                    Peter Barada <peterb@logicpd.com>
   7 *
   8 * Copyright (C) 2007 MontaVista Software, Inc.
   9 *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10 *
  11 * (C) Copyright 2008
  12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13 *
  14 * This program is free software; you can redistribute it and/or
  15 * modify it under the terms of the GNU General Public License as
  16 * published by the Free Software Foundation; either version 2 of
  17 * the License, or (at your option) any later version.
  18 */
  19
  20#ifndef __CONFIG_H
  21#define __CONFIG_H
  22
  23/*
  24 * High Level Configuration Options
  25 */
  26#define CONFIG_E300             1 /* E300 family */
  27#define CONFIG_QE               1 /* Has QE */
  28#define CONFIG_MPC83xx          1 /* MPC83xx family */
  29#define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  30#define CONFIG_KMETER1          1 /* KMETER1 board specific */
  31#define CONFIG_HOSTNAME         kmeter1
  32
  33/* include common defines/options for all Keymile boards */
  34#include "keymile-common.h"
  35
  36#define CONFIG_MISC_INIT_R      1
  37/*
  38 * System Clock Setup
  39 */
  40#define CONFIG_83XX_CLKIN               66000000
  41#define CONFIG_SYS_CLK_FREQ             66000000
  42#define CONFIG_83XX_PCICLK              66000000
  43
  44/*
  45 * Hardware Reset Configuration Word
  46 */
  47#define CONFIG_SYS_HRCW_LOW (\
  48        HRCWL_CSB_TO_CLKIN_4X1 | \
  49        HRCWL_CORE_TO_CSB_2X1 | \
  50        HRCWL_CE_PLL_VCO_DIV_2 | \
  51        HRCWL_CE_TO_PLL_1X6 )
  52
  53#define CONFIG_SYS_HRCW_HIGH (\
  54        HRCWH_CORE_ENABLE | \
  55        HRCWH_FROM_0X00000100 | \
  56        HRCWH_BOOTSEQ_DISABLE | \
  57        HRCWH_SW_WATCHDOG_DISABLE | \
  58        HRCWH_ROM_LOC_LOCAL_16BIT | \
  59        HRCWH_BIG_ENDIAN | \
  60        HRCWH_LALE_EARLY | \
  61        HRCWH_LDP_CLEAR )
  62
  63/*
  64 * System IO Config
  65 */
  66#define CONFIG_SYS_SICRH                0x00000006
  67#define CONFIG_SYS_SICRL                0x00000000
  68
  69/*
  70 * IMMR new address
  71 */
  72#define CONFIG_SYS_IMMR         0xE0000000
  73
  74/*
  75 * DDR Setup
  76 */
  77#define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  78#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  79#define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  80#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  81                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  82
  83#define CFG_83XX_DDR_USES_CS0
  84
  85#undef CONFIG_DDR_ECC
  86
  87/*
  88 * DDRCDR - DDR Control Driver Register
  89 */
  90
  91#undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
  92
  93/*
  94 * Manually set up DDR parameters
  95 */
  96#define CONFIG_DDR_II
  97#define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  98#define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  99#define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 100                                         CSCONFIG_ROW_BIT_13 | \
 101                                         CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
 102
 103#define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 104                                         SDRAM_CFG_SREN)
 105#define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 106#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 107#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 108                                 (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
 109
 110#define CONFIG_SYS_DDRCDR               0x40000001
 111#define CONFIG_SYS_DDR_MODE             0x47860452
 112#define CONFIG_SYS_DDR_MODE2            0x8080c000
 113
 114#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 115                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 116                                 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 117                                 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 118                                 (0 << TIMING_CFG0_WWT_SHIFT) | \
 119                                 (0 << TIMING_CFG0_RRT_SHIFT) | \
 120                                 (0 << TIMING_CFG0_WRT_SHIFT) | \
 121                                 (0 << TIMING_CFG0_RWT_SHIFT))
 122
 123#define CONFIG_SYS_DDR_TIMING_1 ((      TIMING_CFG1_CASLAT_50) | \
 124                                 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 125                                 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 126                                 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
 127                                 ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
 128                                 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 129                                 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 130                                 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 131
 132#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 133                                 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 134                                 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 135                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 136                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 137                                 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 138                                 (5 << TIMING_CFG2_CPO_SHIFT))
 139
 140#define CONFIG_SYS_DDR_TIMING_3 0x00000000
 141
 142/*
 143 * The reserved memory
 144 */
 145#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 146#define CONFIG_SYS_FLASH_BASE           0xF0000000
 147#define CONFIG_SYS_FLASH_BASE_1         0xF2000000
 148#define CONFIG_SYS_PIGGY_BASE           0xE8000000
 149#define CONFIG_SYS_PIGGY_SIZE           128
 150#define CONFIG_SYS_PAXE_BASE            0xA0000000
 151#define CONFIG_SYS_PAXE_SIZE            512
 152
 153#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 154#define CONFIG_SYS_RAMBOOT
 155#else
 156#undef  CONFIG_SYS_RAMBOOT
 157#endif
 158
 159#define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
 160
 161/*
 162 * Initial RAM Base Address Setup
 163 */
 164#define CONFIG_SYS_INIT_RAM_LOCK        1
 165#define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 166#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 167#define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 168#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 169
 170/*
 171 * Local Bus Configuration & Clock Setup
 172 */
 173#define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
 174
 175/*
 176 * Init Local Bus Memory Controller:
 177 *
 178 * Bank Bus     Machine PortSz  Size  Device
 179 * ---- ---     ------- ------  -----  ------
 180 *  0   Local   GPCM    16 bit  256MB FLASH
 181 *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 182 *  3   Local   GPCM     8 bit  512MB PAXE
 183 *
 184 */
 185/*
 186 * FLASH on the Local Bus
 187 */
 188#define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 189#define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 190#define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 191#define CONFIG_SYS_FLASH_PROTECTION     1
 192#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 193
 194#define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 195#define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001b /* 256MB window size */
 196
 197#define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 198                                (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 199                                BR_V)
 200
 201#define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 202                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 203                                OR_GPCM_SCY_5 | \
 204                                OR_GPCM_TRLX | OR_GPCM_EAD)
 205
 206#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks       */
 207#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 208#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
 209
 210#undef  CONFIG_SYS_FLASH_CHECKSUM
 211
 212/*
 213 * PRIO1/PIGGY on the local bus CS1
 214 */
 215#define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
 216#define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001A /* 128MB window size */
 217
 218#define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_PIGGY_BASE | \
 219                                (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 220                                BR_V)
 221#define CONFIG_SYS_OR1_PRELIM           (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
 222                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 223                                OR_GPCM_SCY_2 | \
 224                                OR_GPCM_TRLX | OR_GPCM_EAD)
 225
 226/*
 227 * PAXE on the local bus CS3
 228 */
 229#define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE /* Window base at flash base */
 230#define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 231
 232#define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
 233                                (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 234                                BR_V)
 235#define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 236                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 237                                OR_GPCM_SCY_2 | \
 238                                OR_GPCM_TRLX | OR_GPCM_EAD)
 239
 240/*
 241 * Serial Port
 242 */
 243#define CONFIG_CONS_INDEX       1
 244#undef  CONFIG_SERIAL_SOFTWARE_FIFO
 245#define CONFIG_SYS_NS16550
 246#define CONFIG_SYS_NS16550_SERIAL
 247#define CONFIG_SYS_NS16550_REG_SIZE     1
 248#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 249
 250#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 251#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 252
 253/* Pass open firmware flat tree */
 254#define CONFIG_OF_LIBFDT        1
 255#define CONFIG_OF_BOARD_SETUP   1
 256#define CONFIG_OF_STDOUT_VIA_ALIAS
 257
 258/*
 259 * General PCI
 260 * Addresses are mapped 1-1.
 261 */
 262#undef CONFIG_PCI               /* No PCI */
 263
 264#ifndef CONFIG_NET_MULTI
 265#define CONFIG_NET_MULTI        1
 266#endif
 267/*
 268 * QE UEC ethernet configuration
 269 */
 270#define CONFIG_UEC_ETH
 271#define CONFIG_ETHPRIME         "FSL UEC0"
 272
 273#define CONFIG_UEC_ETH1         /* GETH1 */
 274#define UEC_VERBOSE_DEBUG       1
 275
 276#ifdef CONFIG_UEC_ETH1
 277#define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 278#define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE     /* not used in RMII Mode */
 279#define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 280#define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 281#define CONFIG_SYS_UEC1_PHY_ADDR        0
 282#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
 283#endif
 284
 285/*
 286 * Environment
 287 */
 288
 289#ifndef CONFIG_SYS_RAMBOOT
 290#define CONFIG_ENV_IS_IN_FLASH  1
 291#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 292#define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 293#define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 294
 295/* Address and size of Redundant Environment Sector     */
 296#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 297#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 298
 299#else /* CFG_RAMBOOT */
 300#define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 301#define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 302#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 303#define CONFIG_ENV_SIZE         0x2000
 304#endif /* CFG_RAMBOOT */
 305
 306/* I2C */
 307#define CONFIG_HARD_I2C         /* I2C with hardware support */
 308#undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 309#define CONFIG_FSL_I2C
 310#define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
 311#define CONFIG_SYS_I2C_SLAVE    0x7F
 312#define CONFIG_SYS_I2C_OFFSET   0x3000
 313#define CONFIG_I2C_MULTI_BUS    1
 314#define CONFIG_I2C_MUX          1
 315
 316/* EEprom support */
 317#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 318
 319/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 320#define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 321#define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses             */
 322#define CONFIG_SYS_DTT_MAX_TEMP 70
 323#define CONFIG_SYS_DTT_LOW_TEMP -30
 324#define CONFIG_SYS_DTT_HYSTERESIS       3
 325#define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 326
 327#if defined(CONFIG_PCI)
 328#define CONFIG_CMD_PCI
 329#endif
 330
 331#if defined(CFG_RAMBOOT)
 332#undef CONFIG_CMD_SAVEENV
 333#undef CONFIG_CMD_LOADS
 334#endif
 335
 336/*
 337 * For booting Linux, the board info and command line data
 338 * have to be in the first 8 MB of memory, since this is
 339 * the maximum mapped by the Linux kernel during initialization.
 340 */
 341#define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 342
 343/*
 344 * Core HID Setup
 345 */
 346#define CONFIG_SYS_HID0_INIT            0x000000000
 347#define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 348#define CONFIG_SYS_HID2                 HID2_HBE
 349
 350/*
 351 * MMU Setup
 352 */
 353
 354#define CONFIG_HIGH_BATS        1       /* High BATs supported */
 355
 356/* DDR: cache cacheable */
 357#define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 358                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 359#define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 360#define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 361#define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 362
 363/* IMMRBAR & PCI IO: cache-inhibit and guarded */
 364#define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 365                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 366#define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 367#define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 368#define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 369
 370/* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 371#define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 372#define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 373#define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 374                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 375#define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 376
 377/* FLASH: icache cacheable, but dcache-inhibit and guarded */
 378#define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 379#define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 380#define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 381                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 382#define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 383
 384/* Stack in dcache: cacheable, no memory coherence */
 385#define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 386#define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 387#define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 388#define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 389
 390/* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 391#define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 392#define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 393#define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 394                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 395#define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 396
 397#ifdef CONFIG_PCI
 398/* PCI MEM space: cacheable */
 399#define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 400#define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 401#define CFG_DBAT6L      CFG_IBAT6L
 402#define CFG_DBAT6U      CFG_IBAT6U
 403/* PCI MMIO space: cache-inhibit and guarded */
 404#define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 405                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 406#define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 407#define CFG_DBAT7L      CFG_IBAT7L
 408#define CFG_DBAT7U      CFG_IBAT7U
 409#else /* CONFIG_PCI */
 410#define CONFIG_SYS_IBAT6L       (0)
 411#define CONFIG_SYS_IBAT6U       (0)
 412#define CONFIG_SYS_IBAT7L       (0)
 413#define CONFIG_SYS_IBAT7U       (0)
 414#define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 415#define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 416#define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 417#define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 418#endif /* CONFIG_PCI */
 419
 420/*
 421 * Internal Definitions
 422 *
 423 * Boot Flags
 424 */
 425#define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 426#define BOOTFLAG_WARM   0x02 /* Software reboot */
 427
 428#define BOOTFLASH_START F0000000
 429
 430#define CONFIG_PRAM     512     /* protected RAM [KBytes] */
 431
 432#define MTDIDS_DEFAULT          "nor2=app"
 433#define MTDPARTS_DEFAULT \
 434        "mtdparts=app:256k(u-boot),128k(env),128k(envred),"     \
 435        "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
 436
 437/*
 438 * Environment Configuration
 439 */
 440#define CONFIG_ENV_OVERWRITE
 441#ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 442#define CONFIG_KM_DEF_ENV "km-common=empty\0"
 443#endif
 444
 445#define CONFIG_EXTRA_ENV_SETTINGS \
 446       CONFIG_KM_DEF_ENV                                                \
 447        "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 448        "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 449        "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"                     \
 450        "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"              \
 451        "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"                      \
 452        "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0"                \
 453        "unlock=yes\0"                                                  \
 454        "fdt_addr=F0080000\0"                                           \
 455        "kernel_addr=F00a0000\0"                                        \
 456        "ramdisk_addr=F03a0000\0"                                       \
 457        "ramdisk_addr_r=F10000\0"                                       \
 458        "EEprom_ivm=pca9547:70:9\0"                                     \
 459        "dtt_bus=pca9547:70:a\0"                                        \
 460        "mtdids=nor0=app \0"                                            \
 461        "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
 462   ""
 463
 464#if defined(CONFIG_UEC_ETH)
 465#define CONFIG_HAS_ETH0
 466#endif
 467
 468#endif /* __CONFIG_H */
 469