1/* 2 * (C) Copyright 2002 3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 4 * 5 * (C) Copyright 2002 6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 * Marius Groeger <mgroeger@sysgo.de> 8 * 9 * Configuation settings for the LUBBOCK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ 38#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ 39#define CONFIG_LCD 1 40#ifdef CONFIG_LCD 41#define CONFIG_SHARP_LM8V31 42#endif 43#define CONFIG_MMC 44#define BOARD_LATE_INIT 1 45#define CONFIG_DOS_PARTITION 46 47#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 48 49/* we will never enable dcache, because we have to setup MMU first */ 50#define CONFIG_SYS_NO_DCACHE 51 52/* 53 * Size of malloc() pool 54 */ 55#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 56#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 57 58/* 59 * Hardware drivers 60 */ 61#define CONFIG_DRIVER_LAN91C96 62#define CONFIG_LAN91C96_BASE 0x0C000000 63 64/* 65 * select serial console configuration 66 */ 67#define CONFIG_PXA_SERIAL 68#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ 69 70/* allow to overwrite serial and ethaddr */ 71#define CONFIG_ENV_OVERWRITE 72 73#define CONFIG_BAUDRATE 115200 74 75 76/* 77 * BOOTP options 78 */ 79#define CONFIG_BOOTP_BOOTFILESIZE 80#define CONFIG_BOOTP_BOOTPATH 81#define CONFIG_BOOTP_GATEWAY 82#define CONFIG_BOOTP_HOSTNAME 83 84 85/* 86 * Command line configuration. 87 */ 88#include <config_cmd_default.h> 89 90#define CONFIG_CMD_FAT 91 92 93#define CONFIG_BOOTDELAY 3 94#define CONFIG_ETHADDR 08:00:3e:26:0a:5b 95#define CONFIG_NETMASK 255.255.0.0 96#define CONFIG_IPADDR 192.168.0.21 97#define CONFIG_SERVERIP 192.168.0.250 98#define CONFIG_BOOTCOMMAND "bootm 80000" 99#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" 100#define CONFIG_CMDLINE_TAG 101#define CONFIG_TIMESTAMP 102 103#if defined(CONFIG_CMD_KGDB) 104#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 105#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 106#endif 107 108/* 109 * Miscellaneous configurable options 110 */ 111#define CONFIG_SYS_HUSH_PARSER 1 112#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 113 114#define CONFIG_SYS_LONGHELP /* undef to save memory */ 115#ifdef CONFIG_SYS_HUSH_PARSER 116#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ 117#else 118#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 119#endif 120#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 121#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 122#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 123#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 124#define CONFIG_SYS_DEVICE_NULLDEV 1 125 126#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 127#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 128 129#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ 130 131#define CONFIG_SYS_HZ 1000 132#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ 133 134 /* valid baudrates */ 135#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 136 137#ifdef CONFIG_MMC 138#define CONFIG_PXA_MMC 139#define CONFIG_CMD_MMC 140#define CONFIG_SYS_MMC_BASE 0xF0000000 141#endif 142 143/* 144 * Stack sizes 145 * 146 * The stack sizes are set up in start.S using the settings below 147 */ 148#define CONFIG_STACKSIZE (128*1024) /* regular stack */ 149#ifdef CONFIG_USE_IRQ 150#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 151#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 152#endif 153 154/* 155 * Physical Memory Map 156 */ 157#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ 158#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 159#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 160#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 161#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 162#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 163#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 164#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 165#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 166 167#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 168#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ 169#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 170#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ 171#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ 172 173#define CONFIG_SYS_DRAM_BASE 0xa0000000 174#define CONFIG_SYS_DRAM_SIZE 0x04000000 175 176#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 177 178#define FPGA_REGS_BASE_PHYSICAL 0x08000000 179 180/* 181 * GPIO settings 182 */ 183#define CONFIG_SYS_GPSR0_VAL 0x00008000 184#define CONFIG_SYS_GPSR1_VAL 0x00FC0382 185#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF 186#define CONFIG_SYS_GPCR0_VAL 0x00000000 187#define CONFIG_SYS_GPCR1_VAL 0x00000000 188#define CONFIG_SYS_GPCR2_VAL 0x00000000 189#define CONFIG_SYS_GPDR0_VAL 0x0060A800 190#define CONFIG_SYS_GPDR1_VAL 0x00FF0382 191#define CONFIG_SYS_GPDR2_VAL 0x0001C000 192#define CONFIG_SYS_GAFR0_L_VAL 0x98400000 193#define CONFIG_SYS_GAFR0_U_VAL 0x00002950 194#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558 195#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA 196#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 197#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 198 199#define CONFIG_SYS_PSSR_VAL 0x20 200 201/* 202 * Memory settings 203 */ 204#define CONFIG_SYS_MSC0_VAL 0x23F223F2 205#define CONFIG_SYS_MSC1_VAL 0x3FF1A441 206#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1 207#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9 208#define CONFIG_SYS_MDREFR_VAL 0x00018018 209#define CONFIG_SYS_MDMRS_VAL 0x00000000 210 211/* 212 * PCMCIA and CF Interfaces 213 */ 214#define CONFIG_SYS_MECR_VAL 0x00000000 215#define CONFIG_SYS_MCMEM0_VAL 0x00010504 216#define CONFIG_SYS_MCMEM1_VAL 0x00010504 217#define CONFIG_SYS_MCATT0_VAL 0x00010504 218#define CONFIG_SYS_MCATT1_VAL 0x00010504 219#define CONFIG_SYS_MCIO0_VAL 0x00004715 220#define CONFIG_SYS_MCIO1_VAL 0x00004715 221 222#define _LED 0x08000010 223#define LED_BLANK 0x08000040 224 225/* 226 * FLASH and environment organization 227 */ 228#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 229#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 230 231/* timeout values are in ticks */ 232#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 233#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 234 235/* NOTE: many default partitioning schemes assume the kernel starts at the 236 * second sector, not an environment. You have been warned! 237 */ 238#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 239#define CONFIG_ENV_IS_IN_FLASH 1 240#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) 241#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE 242#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) 243 244 245/* 246 * FPGA Offsets 247 */ 248#define WHOAMI_OFFSET 0x00 249#define HEXLED_OFFSET 0x10 250#define BLANKLED_OFFSET 0x40 251#define DISCRETELED_OFFSET 0x40 252#define CNFG_SWITCHES_OFFSET 0x50 253#define USER_SWITCHES_OFFSET 0x60 254#define MISC_WR_OFFSET 0x80 255#define MISC_RD_OFFSET 0x90 256#define INT_MASK_OFFSET 0xC0 257#define INT_CLEAR_OFFSET 0xD0 258#define GP_OFFSET 0x100 259 260#endif /* __CONFIG_H */ 261