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28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32#define CONFIG_LOGBUFFER
33
34
35
36
37
38
39#define CONFIG_MPC823 1
40#define CONFIG_LWMON 1
41
42
43#define CONFIG_ETHADDR 00:11:B0:00:00:00
44
45
46#ifdef CONFIG_ETHADDR
47#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
48#endif
49
50#define CONFIG_BOARD_EARLY_INIT_F 1
51#define CONFIG_BOARD_POSTCLK_INIT 1
52
53#define CONFIG_LCD 1
54#define CONFIG_HLD1045 1
55
56#define CONFIG_LCD_LOGO 1
57#define CONFIG_LCD_INFO 1
58#define CONFIG_SPLASH_SCREEN
59
60#define CONFIG_SERIAL_MULTI 1
61#define CONFIG_8xx_CONS_SMC2 1
62#define CONFIG_8xx_CONS_SCC2 1
63
64#define CONFIG_BAUDRATE 115200
65
66#define CONFIG_BOOTDELAY 1
67
68#define CONFIG_CLOCKS_IN_MHZ 1
69
70
71#define CONFIG_PREBOOT "setenv bootdelay 15"
72
73#undef CONFIG_BOOTARGS
74
75
76#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
77 CONFIG_SYS_POST_WATCHDOG | \
78 CONFIG_SYS_POST_RTC | \
79 CONFIG_SYS_POST_MEMORY | \
80 CONFIG_SYS_POST_CPU | \
81 CONFIG_SYS_POST_UART | \
82 CONFIG_SYS_POST_ETHER | \
83 CONFIG_SYS_POST_I2C | \
84 CONFIG_SYS_POST_SPI | \
85 CONFIG_SYS_POST_USB | \
86 CONFIG_SYS_POST_SPR | \
87 CONFIG_SYS_POST_SYSMON)
88
89
90
91
92
93
94
95
96#define CONFIG_BOOTCOMMAND "source 40040000;saveenv"
97
98
99#define CONFIG_EXTRA_ENV_SETTINGS \
100 "kernel_addr=40080000\0" \
101 "ramdisk_addr=40280000\0" \
102 "netmask=255.255.192.0\0" \
103 "serverip=10.8.2.101\0" \
104 "ipaddr=10.8.57.0\0" \
105 "magic_keys=#23\0" \
106 "key_magic#=28\0" \
107 "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
108 "key_magic2=3A+3C\0" \
109 "key_cmd2=echo *** Entering Update Mode ***;" \
110 "if fatload ide 0:3 10000 update.scr;" \
111 "then source 10000;" \
112 "else echo *** UPDATE FAILED ***;" \
113 "fi\0" \
114 "key_magic3=3C+3F\0" \
115 "key_cmd3=echo *** Entering Test Mode ***;" \
116 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
117 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
118 "ramargs=setenv bootargs root=/dev/ram rw\0" \
119 "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
120 "addip=setenv bootargs $bootargs " \
121 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
122 "panic=1\0" \
123 "add_wdt=setenv bootargs $bootargs $wdt_args\0" \
124 "add_misc=setenv bootargs $bootargs runmode\0" \
125 "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
126 "bootm $kernel_addr\0" \
127 "flash_self=run ramargs addip add_wdt addfb add_misc;" \
128 "bootm $kernel_addr $ramdisk_addr\0" \
129 "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
130 "run nfsargs addip add_wdt addfb;bootm\0" \
131 "rootpath=/opt/eldk/ppc_8xx\0" \
132 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
133 "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
134 "wdt_args=wdt_8xx=off\0" \
135 "verify=no"
136
137#define CONFIG_LOADS_ECHO 1
138#undef CONFIG_SYS_LOADS_BAUD_CHANGE
139
140#define CONFIG_WATCHDOG 1
141#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 20)
142
143#undef CONFIG_STATUS_LED
144
145
146#undef CONFIG_HARD_I2C
147#define CONFIG_SOFT_I2C 1
148
149#define CONFIG_SYS_I2C_SPEED 93000
150#define CONFIG_SYS_I2C_SLAVE 0xFE
151
152#ifdef CONFIG_SOFT_I2C
153
154
155
156#define PB_SCL 0x00000020
157#define PB_SDA 0x00000010
158
159#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
160#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
161#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
162#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
163#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
164 else immr->im_cpm.cp_pbdat &= ~PB_SDA
165#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
166 else immr->im_cpm.cp_pbdat &= ~PB_SCL
167#define I2C_DELAY udelay(2)
168#endif
169
170
171#define CONFIG_RTC_PCF8563
172
173
174
175
176
177#include <config_cmd_default.h>
178
179#define CONFIG_CMD_ASKENV
180#define CONFIG_CMD_BMP
181#define CONFIG_CMD_BSP
182#define CONFIG_CMD_DATE
183#define CONFIG_CMD_DHCP
184#define CONFIG_CMD_EEPROM
185#define CONFIG_CMD_FAT
186#define CONFIG_CMD_I2C
187#define CONFIG_CMD_IDE
188#define CONFIG_CMD_NFS
189#define CONFIG_CMD_SNTP
190
191#ifdef CONFIG_POST
192#define CONFIG_CMD_DIAG
193#endif
194
195
196#define CONFIG_MAC_PARTITION
197#define CONFIG_DOS_PARTITION
198
199
200
201
202#define CONFIG_BOOTP_SUBNETMASK
203#define CONFIG_BOOTP_GATEWAY
204#define CONFIG_BOOTP_HOSTNAME
205#define CONFIG_BOOTP_BOOTPATH
206#define CONFIG_BOOTP_BOOTFILESIZE
207
208
209
210
211
212#define CONFIG_SYS_LONGHELP
213#define CONFIG_SYS_PROMPT "=> "
214
215#define CONFIG_SYS_HUSH_PARSER 1
216#ifdef CONFIG_SYS_HUSH_PARSER
217#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
218#endif
219
220#if defined(CONFIG_CMD_KGDB)
221#define CONFIG_SYS_CBSIZE 1024
222#else
223#define CONFIG_SYS_CBSIZE 256
224#endif
225#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
226#define CONFIG_SYS_MAXARGS 16
227#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
228
229#define CONFIG_SYS_MEMTEST_START 0x00100000
230#define CONFIG_SYS_MEMTEST_END 0x00F00000
231
232#define CONFIG_SYS_LOAD_ADDR 0x00100000
233
234#define CONFIG_SYS_PIO_MODE 0
235
236#define CONFIG_SYS_HZ 1000
237
238
239
240
241#ifdef CONFIG_WATCHDOG
242#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 57600, 115200 }
243#else
244#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
245#endif
246
247
248#define CONFIG_MODEM_SUPPORT 1
249#undef CONFIG_MODEM_SUPPORT_DEBUG
250
251#define CONFIG_MODEM_KEY_MAGIC "3C+3D"
252#define CONFIG_POST_KEY_MAGIC "3C+3E"
253#if 0
254#define CONFIG_AUTOBOOT_KEYED
255#define CONFIG_AUTOBOOT_PROMPT \
256 "\nEnter password - autoboot in %d sec...\n", bootdelay
257#define CONFIG_AUTOBOOT_DELAY_STR " "
258#endif
259
260
261
262
263
264
265
266
267
268
269#define CONFIG_SYS_IMMR 0xFFF00000
270
271
272
273
274#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
275#define CONFIG_SYS_INIT_RAM_END 0x2F00
276#define CONFIG_SYS_GBL_DATA_SIZE 68
277#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
278#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
279
280
281
282
283
284
285#define CONFIG_SYS_SDRAM_BASE 0x00000000
286#define CONFIG_SYS_FLASH_BASE 0x40000000
287#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
288#define CONFIG_SYS_MONITOR_LEN (256 << 10)
289#else
290#define CONFIG_SYS_MONITOR_LEN (128 << 10)
291#endif
292#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
293#define CONFIG_SYS_MALLOC_LEN (128 << 10)
294
295
296
297
298
299
300#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
301
302
303
304#define CONFIG_SYS_MAX_FLASH_BANKS 2
305#define CONFIG_SYS_MAX_FLASH_SECT 128
306
307#define CONFIG_SYS_FLASH_ERASE_TOUT 180000
308#define CONFIG_SYS_FLASH_WRITE_TOUT 600
309#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
310#define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT 2048
311
312
313
314
315#define CONFIG_SYS_FLASH_BUFFER_SIZE (2*32)
316
317
318#define CONFIG_ENV_IS_IN_FLASH 1
319#define CONFIG_ENV_ADDR 0x40040000
320#define CONFIG_ENV_SIZE 0x2000
321#define CONFIG_ENV_SECT_SIZE 0x40000
322
323
324
325
326
327#define CONFIG_SYS_I2C_AUDIO_ADDR 0x28
328#define CONFIG_SYS_I2C_SYSMON_ADDR 0x2E
329#define CONFIG_SYS_I2C_RTC_ADDR 0x51
330#define CONFIG_SYS_I2C_POWER_A_ADDR 0x52
331#define CONFIG_SYS_I2C_POWER_B_ADDR 0x53
332#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56
333#define CONFIG_SYS_I2C_PICIO_ADDR 0x57
334
335#undef CONFIG_USE_FRAM
336
337#ifdef CONFIG_USE_FRAM
338#define CONFIG_SYS_I2C_EEPROM_ADDR 0x55
339#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
340#else
341#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
342#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
343#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
344#endif
345#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
346
347
348#ifdef CONFIG_USE_FRAM
349#define I2C_ADDR_LIST { \
350 CONFIG_SYS_I2C_SYSMON_ADDR, \
351 CONFIG_SYS_I2C_RTC_ADDR, \
352 CONFIG_SYS_I2C_POWER_A_ADDR, \
353 CONFIG_SYS_I2C_POWER_B_ADDR, \
354 CONFIG_SYS_I2C_KEYBD_ADDR, \
355 CONFIG_SYS_I2C_PICIO_ADDR, \
356 CONFIG_SYS_I2C_EEPROM_ADDR, \
357 }
358#else
359#define I2C_ADDR_LIST { \
360 CONFIG_SYS_I2C_SYSMON_ADDR, \
361 CONFIG_SYS_I2C_RTC_ADDR, \
362 CONFIG_SYS_I2C_POWER_A_ADDR, \
363 CONFIG_SYS_I2C_POWER_B_ADDR, \
364 CONFIG_SYS_I2C_KEYBD_ADDR, \
365 CONFIG_SYS_I2C_PICIO_ADDR, \
366 CONFIG_SYS_I2C_EEPROM_ADDR+0, \
367 CONFIG_SYS_I2C_EEPROM_ADDR+1, \
368 CONFIG_SYS_I2C_EEPROM_ADDR+2, \
369 CONFIG_SYS_I2C_EEPROM_ADDR+3, \
370 CONFIG_SYS_I2C_EEPROM_ADDR+4, \
371 CONFIG_SYS_I2C_EEPROM_ADDR+5, \
372 CONFIG_SYS_I2C_EEPROM_ADDR+6, \
373 CONFIG_SYS_I2C_EEPROM_ADDR+7, \
374 }
375#endif
376
377
378
379
380#define CONFIG_SYS_CACHELINE_SIZE 16
381#if defined(CONFIG_CMD_KGDB)
382#define CONFIG_SYS_CACHELINE_SHIFT 4
383#endif
384
385
386
387
388
389
390
391#if 0 && defined(CONFIG_WATCHDOG)
392#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
393 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
394#else
395#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
396#endif
397
398
399
400
401
402
403
404
405#define CONFIG_SYS_SIUMCR (SIUMCR_GB5E)
406
407
408
409
410
411
412
413#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
414
415
416
417
418
419
420#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
421
422
423
424
425
426
427
428
429#define CONFIG_SYS_PLPRCR_MF 4
430#define CONFIG_SYS_PLPRCR \
431 ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
432 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
433 PLPRCR_LPM_NORMAL | \
434 PLPRCR_CSR \
435 )
436
437#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*13200000)
438
439
440
441
442
443
444
445#define SCCR_MASK SCCR_EBDF11
446
447#define CONFIG_SYS_SCCR (SCCR_COM00 | \
448 SCCR_RTDIV | SCCR_RTSEL | \
449 \
450 SCCR_EBDF00 | SCCR_DFSYNC00 | \
451 SCCR_DFBRG00 | SCCR_DFNL000 | \
452 SCCR_DFNH000 | SCCR_DFLCD100 | \
453 SCCR_DFALCD01)
454
455
456
457
458
459
460#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
461
462
463
464
465
466
467#define CONFIG_SYS_RCCR 0x0000
468
469
470
471
472
473#define CONFIG_SYS_RMDS 0
474
475
476
477
478
479
480#define CONFIG_SYS_CPM_INTERRUPT 13
481
482
483
484
485
486
487#define CONFIG_SYS_PCMCIA_MEM_ADDR (0x50000000)
488#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
489#define CONFIG_SYS_PCMCIA_DMA_ADDR (0x54000000)
490#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
491#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x58000000)
492#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
493#define CONFIG_SYS_PCMCIA_IO_ADDR (0x5C000000)
494#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
495
496
497
498
499
500
501#define CONFIG_IDE_8xx_PCCARD 1
502
503#undef CONFIG_IDE_8xx_DIRECT
504#undef CONFIG_IDE_LED
505#undef CONFIG_IDE_RESET
506
507#define CONFIG_SYS_IDE_MAXBUS 1
508#define CONFIG_SYS_IDE_MAXDEVICE 1
509
510#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
511
512#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
513
514
515#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
516
517
518#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
519
520
521#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
522
523#define CONFIG_SUPPORT_VFAT
524
525
526
527
528
529
530#define CONFIG_SYS_DER 0
531
532
533
534
535
536
537
538#define FLASH_BASE0_PRELIM 0x40000000
539#define FLASH_BASE1_PRELIM 0x41000000
540
541
542
543
544
545#define CONFIG_SYS_REMAP_OR_AM 0xFF000000
546#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000
547
548
549#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK)
550
551#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
552 CONFIG_SYS_OR_TIMING_FLASH)
553#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
554 CONFIG_SYS_OR_TIMING_FLASH)
555
556#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
557
558#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
559#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
560#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
561
562
563
564
565
566
567#define SDRAM_BASE3_PRELIM 0x00000000
568#define SDRAM_PRELIM_OR_AM 0xF0000000
569#define SDRAM_TIMING OR_SCY_0_CLK
570
571#define SDRAM_MAX_SIZE 0x08000000
572
573#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
574#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
575
576
577
578
579
580
581#define TOUCHPNL_BASE 0x20000000
582#define TOUCHPNL_OR_AM 0xFFFF8000
583#define TOUCHPNL_TIMING OR_SCY_0_CLK
584
585#define CONFIG_SYS_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
586 TOUCHPNL_TIMING )
587#define CONFIG_SYS_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
588
589#define CONFIG_SYS_MEMORY_75
590#undef CONFIG_SYS_MEMORY_7E
591#undef CONFIG_SYS_MEMORY_8E
592
593
594
595
596
597
598#define CONFIG_SYS_MPTPR 0x200
599
600
601
602
603
604#define CONFIG_SYS_MAMR_8COL 0x80802114
605#define CONFIG_SYS_MAMR_9COL 0x80904114
606
607
608
609
610#define CONFIG_SYS_MAR 0x00000088
611
612
613
614
615
616
617#define BOOTFLAG_COLD 0x01
618#define BOOTFLAG_WARM 0x02
619
620#endif
621