LXR uboot/include/configs/pcs440ep.h

   1/*
   2 * (C) Copyright 2006
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/************************************************************************
  25 * pcs440ep.h - configuration for PCS440EP board
  26 ***********************************************************************/
  27#ifndef __CONFIG_H
  28#define __CONFIG_H
  29
  30
  31/* new uImage format support */
  32#define CONFIG_FIT              1
  33#define CONFIG_OF_LIBFDT        1
  34#define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
  35
  36/*-----------------------------------------------------------------------
  37 * High Level Configuration Options
  38 *----------------------------------------------------------------------*/
  39#define CONFIG_PCS440EP         1       /* Board is PCS440EP            */
  40#define CONFIG_440EP            1       /* Specific PPC440EP support    */
  41#define CONFIG_440              1       /* ... PPC440 family            */
  42#define CONFIG_4xx              1       /* ... PPC4xx family            */
  43#define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  44
  45#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  46#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  47
  48/*-----------------------------------------------------------------------
  49 * Base addresses -- Note these are effective addresses where the
  50 * actual resources get mapped (not physical addresses)
  51 *----------------------------------------------------------------------*/
  52#define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384 kB for Monitor   */
  53#define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
  54#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
  55#define CONFIG_SYS_SDRAM_BASE           0x00000000          /* _must_ be 0      */
  56#define CONFIG_SYS_FLASH_BASE           0xfff00000          /* start of FLASH   */
  57#define CONFIG_SYS_PCI_MEMBASE          0xa0000000          /* mapped pci memory*/
  58#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  59#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  60#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  61
  62/*Don't change either of these*/
  63#define CONFIG_SYS_PERIPHERAL_BASE     0xef600000           /* internal peripherals*/
  64#define CONFIG_SYS_PCI_BASE             0xe0000000          /* internal PCI regs*/
  65/*Don't change either of these*/
  66
  67#define CONFIG_SYS_USB_DEVICE          0x50000000
  68#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
  69
  70/*-----------------------------------------------------------------------
  71 * Initial RAM & stack pointer (placed in SDRAM)
  72 *----------------------------------------------------------------------*/
  73#define CONFIG_SYS_INIT_RAM_DCACHE      1               /* d-cache as init ram  */
  74#define CONFIG_SYS_INIT_RAM_ADDR        0x70000000              /* DCache       */
  75#define CONFIG_SYS_INIT_RAM_END (4 << 10)
  76#define CONFIG_SYS_GBL_DATA_SIZE        256                     /* num bytes initial data*/
  77#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  78#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  79
  80/*-----------------------------------------------------------------------
  81 * Serial Port
  82 *----------------------------------------------------------------------*/
  83#undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* no external clk used         */
  84#define CONFIG_BAUDRATE         115200
  85#define CONFIG_SERIAL_MULTI     1
  86/*define this if you want console on UART1*/
  87#undef CONFIG_UART1_CONSOLE
  88
  89#define CONFIG_SYS_BAUDRATE_TABLE  \
  90    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  91
  92/*-----------------------------------------------------------------------
  93 * Environment
  94 *----------------------------------------------------------------------*/
  95#define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  96
  97/*-----------------------------------------------------------------------
  98 * FLASH related
  99 *----------------------------------------------------------------------*/
 100#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 101#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 102
 103#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 104#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 105
 106#define CONFIG_SYS_FLASH_WORD_SIZE      unsigned char   /* flash word size (width)      */
 107#define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 108#define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 109
 110#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 111
 112#ifdef CONFIG_ENV_IS_IN_FLASH
 113#define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector          */
 114#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 115#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 116
 117#define CONFIG_ENV_OVERWRITE    1
 118
 119/* Address and size of Redundant Environment Sector     */
 120#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 121#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 122#endif /* CONFIG_ENV_IS_IN_FLASH */
 123
 124#define ENV_NAME_REVLEV "revision_level"
 125#define ENV_NAME_SOLDER "solder_switch"
 126#define ENV_NAME_DIP    "dip"
 127
 128/*-----------------------------------------------------------------------
 129 * DDR SDRAM
 130 *----------------------------------------------------------------------*/
 131#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 132#undef CONFIG_DDR_ECC                   /* don't use ECC                        */
 133#define SPD_EEPROM_ADDRESS      {0x50}
 134#define CONFIG_PROG_SDRAM_TLB   1
 135
 136/*-----------------------------------------------------------------------
 137 * I2C
 138 *----------------------------------------------------------------------*/
 139#define CONFIG_HARD_I2C         1           /* I2C with hardware support        */
 140#undef  CONFIG_SOFT_I2C                     /* I2C bit-banged           */
 141#define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 142#define CONFIG_SYS_I2C_SLAVE            0x7F
 143
 144#define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa4>>1)
 145#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 146#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 147#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 148
 149#define CONFIG_PREBOOT  "echo;" \
 150        "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 151        "echo"
 152
 153#undef  CONFIG_BOOTARGS
 154
 155#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 156        "netdev=eth0\0"                                                 \
 157        "hostname=pcs440ep\0"                                           \
 158        "use_eeprom_ethaddr=default\0"                                  \
 159        "cs_test=off\0"                                                 \
 160        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 161                "nfsroot=${serverip}:${rootpath}\0"                     \
 162        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 163        "addip=setenv bootargs ${bootargs} "                            \
 164                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 165                ":${hostname}:${netdev}:off panic=1\0"                  \
 166        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 167        "flash_nfs=run nfsargs addip addtty;"                           \
 168                "bootm ${kernel_addr}\0"                                \
 169        "flash_self=run ramargs addip addtty;"                          \
 170                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 171        "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 172                "bootm\0"                                               \
 173        "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 174        "bootfile=/tftpboot/pcs440ep/uImage\0"                          \
 175        "kernel_addr=FFF00000\0"                                        \
 176        "ramdisk_addr=FFF00000\0"                                       \
 177        "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0"              \
 178        "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 179                "cp.b 100000 FFFA0000 60000\0"                          \
 180        "upd=run load update\0"                                         \
 181        ""
 182#define CONFIG_BOOTCOMMAND      "run flash_self"
 183
 184#if 0
 185#define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 186#else
 187#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 188#endif
 189
 190/* check U-Boot image with SHA1 sum */
 191#define CONFIG_SHA1_CHECK_UB_IMG        1
 192#define CONFIG_SHA1_START               CONFIG_SYS_MONITOR_BASE
 193#define CONFIG_SHA1_LEN                 CONFIG_SYS_MONITOR_LEN
 194
 195/*-----------------------------------------------------------------------
 196 * Definitions for status LED
 197 */
 198#define CONFIG_STATUS_LED       1       /* Status LED enabled           */
 199#define CONFIG_BOARD_SPECIFIC_LED       1
 200
 201#define STATUS_LED_BIT          0x08                    /* DIAG1 is on GPIO_PPC_1 */
 202#define STATUS_LED_PERIOD       ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
 203#define STATUS_LED_STATE        STATUS_LED_OFF
 204#define STATUS_LED_BIT1         0x04                    /* DIAG2 is on GPIO_PPC_2 */
 205#define STATUS_LED_PERIOD1      ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
 206#define STATUS_LED_STATE1       STATUS_LED_ON
 207#define STATUS_LED_BIT2         0x02                    /* DIAG3 is on GPIO_PPC_3 */
 208#define STATUS_LED_PERIOD2      ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
 209#define STATUS_LED_STATE2       STATUS_LED_OFF
 210#define STATUS_LED_BIT3         0x01                    /* DIAG4 is on GPIO_PPC_4 */
 211#define STATUS_LED_PERIOD3      ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
 212#define STATUS_LED_STATE3       STATUS_LED_OFF
 213
 214#define CONFIG_SHOW_BOOT_PROGRESS       1
 215
 216#define CONFIG_BAUDRATE         115200
 217
 218#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 219#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 220
 221#define CONFIG_PPC4xx_EMAC
 222#define CONFIG_MII              1       /* MII PHY management           */
 223#define CONFIG_NET_MULTI        1       /* required for netconsole      */
 224#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 225#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 226#define CONFIG_PHY1_ADDR        2
 227
 228#define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 229
 230#define CONFIG_NETCONSOLE               /* include NetConsole support   */
 231
 232/* Partitions */
 233#define CONFIG_MAC_PARTITION
 234#define CONFIG_DOS_PARTITION
 235#define CONFIG_ISO_PARTITION
 236
 237#ifdef CONFIG_440EP
 238/* USB */
 239#define CONFIG_USB_OHCI
 240#define CONFIG_USB_STORAGE
 241
 242/*Comment this out to enable USB 1.1 device*/
 243#define USB_2_0_DEVICE
 244#endif /*CONFIG_440EP*/
 245
 246#ifdef DEBUG
 247#define CONFIG_PANIC_HANG
 248#else
 249#define CONFIG_HW_WATCHDOG                      /* watchdog */
 250#endif
 251
 252
 253/*
 254 * BOOTP options
 255 */
 256#define CONFIG_BOOTP_BOOTFILESIZE
 257#define CONFIG_BOOTP_BOOTPATH
 258#define CONFIG_BOOTP_GATEWAY
 259#define CONFIG_BOOTP_HOSTNAME
 260
 261
 262/*
 263 * Command line configuration.
 264 */
 265#include <config_cmd_default.h>
 266#define CONFIG_CMD_ASKENV
 267#define CONFIG_CMD_DHCP
 268#define CONFIG_CMD_DIAG
 269#define CONFIG_CMD_EEPROM
 270#define CONFIG_CMD_ELF
 271#define CONFIG_CMD_EXT2
 272#define CONFIG_CMD_FAT
 273#define CONFIG_CMD_I2C
 274#define CONFIG_CMD_IDE
 275#define CONFIG_CMD_IRQ
 276#define CONFIG_CMD_MII
 277#define CONFIG_CMD_NET
 278#define CONFIG_CMD_NFS
 279#define CONFIG_CMD_PCI
 280#define CONFIG_CMD_PING
 281#define CONFIG_CMD_REGINFO
 282#define CONFIG_CMD_REISER
 283#define CONFIG_CMD_SDRAM
 284#define CONFIG_CMD_USB
 285
 286#define CONFIG_SUPPORT_VFAT
 287
 288/*
 289 * Miscellaneous configurable options
 290 */
 291#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 292#define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 293#if defined(CONFIG_CMD_KGDB)
 294#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 295#else
 296#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 297#endif
 298#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 299#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 300#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 301
 302#define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 303#define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 304
 305#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 306#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 307#define CONFIG_LYNXKDI          1       /* support kdi files            */
 308
 309#define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 310
 311/*-----------------------------------------------------------------------
 312 * PCI stuff
 313 *-----------------------------------------------------------------------
 314 */
 315/* General PCI */
 316#define CONFIG_PCI                      /* include pci support          */
 317#undef  CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 318#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 319#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 320
 321/* Board-specific PCI */
 322#define CONFIG_SYS_PCI_TARGET_INIT
 323#define CONFIG_SYS_PCI_MASTER_INIT
 324
 325#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 326#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever */
 327
 328/*
 329 * For booting Linux, the board info and command line data
 330 * have to be in the first 8 MB of memory, since this is
 331 * the maximum mapped by the Linux kernel during initialization.
 332 */
 333#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 334
 335/*-----------------------------------------------------------------------
 336 * External Bus Controller (EBC) Setup
 337 *----------------------------------------------------------------------*/
 338#define FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank #0        */
 339#define FLASH_BASE1_PRELIM      0xFFF80000      /* FLASH bank #1        */
 340
 341#define CONFIG_SYS_FLASH                FLASH_BASE0_PRELIM
 342#define CONFIG_SYS_SRAM         0xF1000000
 343#define CONFIG_SYS_FPGA         0xF2000000
 344#define CONFIG_SYS_CF1                  0xF0000000
 345#define CONFIG_SYS_CF2                  0xF0100000
 346
 347/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 348#define CONFIG_SYS_EBC_PB0AP            0x02010000      /* TWT=4,OEN=1                  */
 349#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit   */
 350
 351/* Memory Bank 1 (SRAM) initialization                                          */
 352#define CONFIG_SYS_EBC_PB1AP            0x01810040      /* TWT=3,OEN=1,BEM=1            */
 353#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit   */
 354
 355/* Memory Bank 2 (FPGA) initialization                                          */
 356#define CONFIG_SYS_EBC_PB2AP            0x01010440      /* TWT=2,OEN=1,TH=2,BEM=1       */
 357#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit   */
 358
 359/* Memory Bank 3 (CompactFlash) initialization                                  */
 360#define CONFIG_SYS_EBC_PB3AP            0x080BD400
 361#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit    */
 362
 363/* Memory Bank 4 (CompactFlash) initialization                                  */
 364#define CONFIG_SYS_EBC_PB4AP            0x080BD400
 365#define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit    */
 366
 367/*-----------------------------------------------------------------------
 368 * PPC440 GPIO Configuration
 369 */
 370#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out                  GPIO     Alternate1      Alternate2   Alternate3 */ \
 371{                                                                                       \
 372/* GPIO Core 0 */                                                                       \
 373{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO0    EBC_ADDR(7)     DMA_REQ(2)      */ \
 374{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO1    EBC_ADDR(6)     DMA_ACK(2)      */      \
 375{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO2    EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 376{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO3    EBC_ADDR(4)     DMA_REQ(3)      */      \
 377{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO4    EBC_ADDR(3)     DMA_ACK(3)      */      \
 378{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO5    EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 379{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6    EBC_CS_N(1)                     */      \
 380{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7    EBC_CS_N(2)                     */      \
 381{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8    EBC_CS_N(3)                     */      \
 382{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9    EBC_CS_N(4)                     */      \
 383{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO10   EBC_CS_N(5)                     */      \
 384{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO11   EBC_BUS_ERR                     */      \
 385{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12   ZII_p0Rxd(0)                    */      \
 386{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13   ZII_p0Rxd(1)                    */      \
 387{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14   ZII_p0Rxd(2)                    */      \
 388{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15   ZII_p0Rxd(3)                    */      \
 389{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16   ZII_p0Txd(0)                    */      \
 390{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17   ZII_p0Txd(1)                    */      \
 391{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18   ZII_p0Txd(2)                    */      \
 392{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19   ZII_p0Txd(3)                    */      \
 393{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20   ZII_p0Rx_er                     */      \
 394{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21   ZII_p0Rx_dv                     */      \
 395{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22   ZII_p0RxCrs                     */      \
 396{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23   ZII_p0Tx_er                     */      \
 397{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24   ZII_p0Tx_en                     */      \
 398{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25   ZII_p0Col                       */      \
 399{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO26                   USB2D_RXVALID   */      \
 400{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO27   EXT_EBC_REQ     USB2D_RXERROR   */      \
 401{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO28                   USB2D_TXVALID   */      \
 402{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO29   EBC_EXT_HDLA    USB2D_PAD_SUSPNDM */    \
 403{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO30   EBC_EXT_ACK     USB2D_XCVRSELECT*/      \
 404{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO31   EBC_EXR_BUSREQ  USB2D_TERMSELECT*/      \
 405},                                                                                      \
 406{                                                                                       \
 407/* GPIO Core 1 */                                                                       \
 408{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO32   USB2D_OPMODE0                   */      \
 409{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO33   USB2D_OPMODE1                   */      \
 410{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34   UART0_DCD_N     UART1_DSR_CTS_N UART2_SOUT*/ \
 411{GPIO1_BASE, GPIO_IN,  GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35   UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 412{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36   UART0_8PIN_CTS_N                UART3_SIN*/ \
 413{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37   UART0_RTS_N                     */      \
 414{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38   UART0_DTR_N     UART1_SOUT      */      \
 415{GPIO1_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39   UART0_RI_N      UART1_SIN       */      \
 416{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40   UIC_IRQ(0)                      */      \
 417{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41   UIC_IRQ(1)                      */      \
 418{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42   UIC_IRQ(2)                      */      \
 419{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43   UIC_IRQ(3)                      */      \
 420{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44   UIC_IRQ(4)      DMA_ACK(1)      */      \
 421{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO45   UIC_IRQ(6)      DMA_EOT/TC(1)   */      \
 422{GPIO1_BASE, GPIO_BI,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO46   UIC_IRQ(7)      DMA_REQ(0)      */      \
 423{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO47   UIC_IRQ(8)      DMA_ACK(0)      */      \
 424{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO48   UIC_IRQ(9)      DMA_EOT/TC(0)   */      \
 425{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO49  Unselect via TraceSelect Bit     */      \
 426{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO50  Unselect via TraceSelect Bit     */      \
 427{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO51  Unselect via TraceSelect Bit     */      \
 428{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO52  Unselect via TraceSelect Bit     */      \
 429{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO53  Unselect via TraceSelect Bit     */      \
 430{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO54  Unselect via TraceSelect Bit     */      \
 431{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO55  Unselect via TraceSelect Bit     */      \
 432{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO56  Unselect via TraceSelect Bit     */      \
 433{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO57  Unselect via TraceSelect Bit     */      \
 434{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO58  Unselect via TraceSelect Bit     */      \
 435{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO59  Unselect via TraceSelect Bit     */      \
 436{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO60  Unselect via TraceSelect Bit     */      \
 437{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO61  Unselect via TraceSelect Bit     */      \
 438{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO62  Unselect via TraceSelect Bit     */      \
 439{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO63  Unselect via TraceSelect Bit     */      \
 440}                                                                                       \
 441}
 442
 443/*
 444 * Internal Definitions
 445 *
 446 * Boot Flags
 447 */
 448#define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 449#define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 450
 451#if defined(CONFIG_CMD_KGDB)
 452#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 453#define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 454#endif
 455
 456/*-----------------------------------------------------------------------
 457 * IDE/ATA stuff Supports IDE harddisk
 458 *-----------------------------------------------------------------------
 459 */
 460
 461#undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 462
 463#undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 464#undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 465
 466#define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 467#define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 2 drives per IDE bus    */
 468
 469#define CONFIG_IDE_PREINIT      1
 470#define CONFIG_IDE_RESET        1
 471
 472#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 473
 474#define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF1
 475
 476/* Offset for data I/O                  */
 477#define CONFIG_SYS_ATA_DATA_OFFSET      0
 478
 479/* Offset for normal register accesses  */
 480#define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 481
 482/* Offset for alternate registers       */
 483#define CONFIG_SYS_ATA_ALT_OFFSET       (0x0000)
 484
 485#endif  /* __CONFIG_H */
 486