1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * Workaround for layout bug on prototype board 33 */ 34#define PCU_E_WITH_SWAPPED_CS 1 35 36/* 37 * High Level Configuration Options 38 * (easy to change) 39 */ 40 41#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ 42#define CONFIG_MPC860T 1 43#define CONFIG_PCU_E 1 /* ...on a PCU E board */ 44 45#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 46 47#define CONFIG_BAUDRATE 9600 48#if 0 49#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 50#else 51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 52#endif 53 54#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 55 56#undef CONFIG_BOOTARGS 57#define CONFIG_BOOTCOMMAND \ 58 "bootp;" \ 59 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ 61 "bootm" 62 63#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 64#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 65 66#undef CONFIG_WATCHDOG /* watchdog disabled */ 67 68#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 69 70#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ 71 72#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 73 74#define CONFIG_SPI /* enable SPI driver */ 75#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ 76 77#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 78#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 79#define CONFIG_SYS_I2C_SLAVE 0x7F 80 81 82/* ---------------------------------------------------------------- 83 * Offset to initial SPI buffers in DPRAM (used if the environment 84 * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to 85 * use at an early stage. It is used between the two initialization 86 * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it 87 * far enough from the start of the data area (as well as from the 88 * stack pointer). 89 * ---------------------------------------------------------------- */ 90#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 91 92 93/* 94 * Command line configuration. 95 */ 96#include <config_cmd_default.h> 97#define CONFIG_CMD_BSP 98#define CONFIG_CMD_DATE 99#define CONFIG_CMD_DHCP 100#define CONFIG_CMD_EEPROM 101#define CONFIG_CMD_NFS 102#define CONFIG_CMD_SNTP 103 104 105/* 106 * BOOTP options 107 */ 108#define CONFIG_BOOTP_SUBNETMASK 109#define CONFIG_BOOTP_HOSTNAME 110#define CONFIG_BOOTP_BOOTPATH 111#define CONFIG_BOOTP_BOOTFILESIZE 112 113 114/* 115 * Miscellaneous configurable options 116 */ 117#define CONFIG_SYS_LONGHELP /* undef to save memory */ 118#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 119#if defined(CONFIG_CMD_KGDB) 120#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 121#else 122#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 123#endif 124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 125#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 127 128#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 129#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ 130 131#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 132 133#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ 134 135/* Ethernet hardware configuration done using port pins */ 136#define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */ 137#if PCU_E_WITH_SWAPPED_CS /* XXX */ 138#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */ 139#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ 140#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */ 141#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */ 142#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */ 143#else /* XXX */ 144#define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */ 145#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ 146#define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */ 147#define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */ 148#define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */ 149#endif /* XXX */ 150 151/* Ethernet settings: 152 * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex 153 */ 154#define CONFIG_SYS_ETH_MDDIS_VALUE 0 155#define CONFIG_SYS_ETH_CFG1_VALUE 1 156#define CONFIG_SYS_ETH_CFG2_VALUE 1 157#define CONFIG_SYS_ETH_CFG3_VALUE 1 158 159/* PUMA configuration */ 160#if PCU_E_WITH_SWAPPED_CS /* XXX */ 161#define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */ 162#else /* XXX */ 163#define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */ 164#endif /* XXX */ 165#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */ 166#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */ 167 168#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 169 170#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 171 172/* 173 * Low Level Configuration Settings 174 * (address mappings, register initial values, etc.) 175 * You should know what you are doing if you make changes here. 176 */ 177/*----------------------------------------------------------------------- 178 * Internal Memory Mapped Register 179 */ 180#define CONFIG_SYS_IMMR 0xFE000000 181 182/*----------------------------------------------------------------------- 183 * Definitions for initial stack pointer and data area (in DPRAM) 184 */ 185#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 186#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 187#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 188#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 189#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 190 191/*----------------------------------------------------------------------- 192 * Address accessed to reset the board - must not be mapped/assigned 193 */ 194#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF 195 196/*----------------------------------------------------------------------- 197 * Start addresses for the final memory configuration 198 * (Set up by the startup code) 199 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 200 */ 201#define CONFIG_SYS_SDRAM_BASE 0x00000000 202/* this is an ugly hack needed because of the silly non-constant address map */ 203#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size) 204 205#if defined(DEBUG) 206#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 207#else 208#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 209#endif 210#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 211#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 212 213/* 214 * For booting Linux, the board info and command line data 215 * have to be in the first 8 MB of memory, since this is 216 * the maximum mapped by the Linux kernel during initialization. 217 */ 218#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 219/*----------------------------------------------------------------------- 220 * FLASH organization 221 */ 222#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 223#define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */ 224 225#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ 226#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ 227 228#if 0 229/* Start port with environment in flash; switch to SPI EEPROM later */ 230#define CONFIG_ENV_IS_IN_FLASH 1 231#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */ 232#define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */ 233#define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */ 234#define CONFIG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ 235#else 236/* Final version: environment in EEPROM */ 237#define CONFIG_ENV_IS_IN_EEPROM 1 238#define CONFIG_SYS_I2C_EEPROM_ADDR 0 239#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 240#define CONFIG_ENV_OFFSET 1024 241#define CONFIG_ENV_SIZE 1024 242#endif 243 244/*----------------------------------------------------------------------- 245 * Cache Configuration 246 */ 247#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 248#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 249#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before 250 * running in RAM. 251 */ 252 253/*----------------------------------------------------------------------- 254 * SYPCR - System Protection Control 11-9 255 * SYPCR can only be written once after reset! 256 *----------------------------------------------------------------------- 257 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 258 */ 259#if defined(CONFIG_WATCHDOG) 260#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 261 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 262#else 263#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 264#endif 265 266/*----------------------------------------------------------------------- 267 * SIUMCR - SIU Module Configuration 11-6 268 *----------------------------------------------------------------------- 269 * External Arbitration max. priority (7), 270 * Debug pins configuration '11', 271 * Asynchronous external master enable. 272 */ 273/* => 0x70600200 */ 274#define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME) 275 276/*----------------------------------------------------------------------- 277 * TBSCR - Time Base Status and Control 11-26 278 *----------------------------------------------------------------------- 279 * Clear Reference Interrupt Status, Timebase freezing enabled 280 */ 281#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 282 283/*----------------------------------------------------------------------- 284 * PISCR - Periodic Interrupt Status and Control 11-31 285 *----------------------------------------------------------------------- 286 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 287 */ 288#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 289 290/*----------------------------------------------------------------------- 291 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 292 *----------------------------------------------------------------------- 293 * Reset PLL lock status sticky bit, timer expired status bit and timer 294 * interrupt status bit, set PLL multiplication factor ! 295 */ 296/* 0x00004080 */ 297#define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */ 298#define CONFIG_SYS_PLPRCR \ 299 ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ 300 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ 301 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ 302 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ 303 ) 304 305#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000) 306 307/*----------------------------------------------------------------------- 308 * SCCR - System Clock and reset Control Register 15-27 309 *----------------------------------------------------------------------- 310 * Set clock output, timebase and RTC source and divider, 311 * power management and some other internal clocks 312 * 313 * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz 314 */ 315#define SCCR_MASK SCCR_EBDF11 316/* 0x01800000 */ 317#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ 318 SCCR_RTDIV | SCCR_RTSEL | \ 319 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ 320 SCCR_EBDF00 | SCCR_DFSYNC00 | \ 321 SCCR_DFBRG00 | SCCR_DFNL000 | \ 322 SCCR_DFNH000 | SCCR_DFLCD100 | \ 323 SCCR_DFALCD01) 324 325/*----------------------------------------------------------------------- 326 * RTCSC - Real-Time Clock Status and Control Register 11-27 327 *----------------------------------------------------------------------- 328 * 329 * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!! 330 * 331 * Don't expect the "date" command to work without a 32kHz clock input! 332 */ 333/* 0x00C3 => 0x0003 */ 334#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 335 336 337/*----------------------------------------------------------------------- 338 * RCCR - RISC Controller Configuration Register 19-4 339 *----------------------------------------------------------------------- 340 */ 341#define CONFIG_SYS_RCCR 0x0000 342 343/*----------------------------------------------------------------------- 344 * RMDS - RISC Microcode Development Support Control Register 345 *----------------------------------------------------------------------- 346 */ 347#define CONFIG_SYS_RMDS 0 348 349/*----------------------------------------------------------------------- 350 * 351 * Interrupt Levels 352 *----------------------------------------------------------------------- 353 */ 354#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ 355 356/*----------------------------------------------------------------------- 357 * 358 *----------------------------------------------------------------------- 359 * 360 */ 361#define CONFIG_SYS_DER 0 362 363/* 364 * Init Memory Controller: 365 * 366 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional 367 */ 368 369#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ 370#if PCU_E_WITH_SWAPPED_CS /* XXX */ 371#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */ 372#else /* XXX */ 373#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */ 374#endif /* XXX */ 375 376/* 377 * used to re-map FLASH: restrict access enough but not too much to 378 * meddle with FLASH accesses 379 */ 380#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ 381#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ 382 383/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */ 384#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR) 385 386#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \ 387 CONFIG_SYS_OR_TIMING_FLASH) 388#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ 389 CONFIG_SYS_OR_TIMING_FLASH) 390/* 16 bit, bank valid */ 391#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) 392 393#if PCU_E_WITH_SWAPPED_CS /* XXX */ 394#define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP 395#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM 396#define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) 397#else /* XXX */ 398#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 399#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 400#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) 401#endif /* XXX */ 402 403/* 404 * BR2/OR2: SDRAM 405 * 406 * Multiplexed addresses, GPL5 output to GPL5_A (don't care) 407 */ 408#if PCU_E_WITH_SWAPPED_CS /* XXX */ 409#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */ 410#else /* XXX */ 411#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */ 412#endif /* XXX */ 413#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */ 414#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */ 415 416#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ 417 418#if PCU_E_WITH_SWAPPED_CS /* XXX */ 419#define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) 420#define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 421#else /* XXX */ 422#define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) 423#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 424#endif /* XXX */ 425 426/* 427 * BR3/OR3: CAN Controller 428 * BR3: 0x10000401 OR3: 0xffff818a 429 */ 430#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */ 431#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */ 432#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR) 433 434#if PCU_E_WITH_SWAPPED_CS /* XXX */ 435#define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) 436#define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) 437#else /* XXX */ 438#define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) 439#define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) 440#endif /* XXX */ 441 442/* 443 * BR4/OR4: PUMA Config 444 * 445 * Memory controller will be used in 2 modes: 446 * 447 * - "read" mode: 448 * BR4: 0x10100801 OR4: 0xffff8530 449 * - "load" mode (chip select on UPM B): 450 * BR4: 0x101008c1 OR4: 0xffff8630 451 * 452 * Default initialization is in "read" mode 453 */ 454#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ 455#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ 456#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK) 457#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK) 458 459#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ 460 BR_PS_16 | BR_MS_UPMB | BR_V) 461#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) 462 463#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) 464#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) 465 466#if PCU_E_WITH_SWAPPED_CS /* XXX */ 467#define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ 468#define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ 469#else /* XXX */ 470#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ 471#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ 472#endif /* XXX */ 473 474/* 475 * BR5/OR5: PUMA: SMA Bus 8 Bit 476 * BR5: 0x10200401 OR5: 0xffe0010a 477 */ 478#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ 479#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ 480#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) 481 482#if PCU_E_WITH_SWAPPED_CS /* XXX */ 483#define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) 484#define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) 485#else /* XXX */ 486#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) 487#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) 488#endif /* XXX */ 489 490/* 491 * BR6/OR6: PUMA: SMA Bus 16 Bit 492 * BR6: 0x10600801 OR6: 0xffe0010a 493 */ 494#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ 495#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ 496#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) 497 498#if PCU_E_WITH_SWAPPED_CS /* XXX */ 499#define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) 500#define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) 501#else /* XXX */ 502#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) 503#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) 504#endif /* XXX */ 505 506/* 507 * BR7/OR7: PUMA: external Flash 508 * BR7: 0x10a00801 OR7: 0xfe00010a 509 */ 510#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ 511#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ 512#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) 513 514#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) 515#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) 516 517/* 518 * Memory Periodic Timer Prescaler 519 */ 520 521/* periodic timer for refresh */ 522#define CONFIG_SYS_MPTPR 0x0200 523 524/* 525 * MAMR settings for SDRAM 526 * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10, 527 * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X 528 * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X 529 */ 530/* periodic timer for refresh */ 531#define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */ 532 533#define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \ 534 MAMR_AMA_TYPE_1 | \ 535 MAMR_G0CLA_A10 | \ 536 MAMR_RLFA_1X | \ 537 MAMR_WLFA_1X | \ 538 MAMR_TLFA_8X ) 539 540/* 541 * Internal Definitions 542 * 543 * Boot Flags 544 */ 545#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 546#define BOOTFLAG_WARM 0x02 /* Software reboot */ 547 548#endif /* __CONFIG_H */ 549