LXR uboot/include/ppc4xx.h

   1/*----------------------------------------------------------------------------+
   2|       This source code is dual-licensed.  You may use it under the terms of
   3|       the GNU General Public License version 2, or under the license below.
   4|
   5|       This source code has been made available to you by IBM on an AS-IS
   6|       basis.  Anyone receiving this source is licensed under IBM
   7|       copyrights to use it in any way he or she deems fit, including
   8|       copying it, modifying it, compiling it, and redistributing it either
   9|       with or without modifications.  No license under IBM patents or
  10|       patent applications is to be implied by the copyright license.
  11|
  12|       Any user of this software should understand that IBM cannot provide
  13|       technical support for this software and will not be responsible for
  14|       any consequences resulting from the use of this software.
  15|
  16|       Any person who transfers this source code or any derivative work
  17|       must include the IBM copyright notice, this paragraph, and the
  18|       preceding two paragraphs in the transferred software.
  19|
  20|       COPYRIGHT   I B M   CORPORATION 1999
  21|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  22+----------------------------------------------------------------------------*/
  23
  24#ifndef __PPC4XX_H__
  25#define __PPC4XX_H__
  26
  27/*
  28 * Configure which SDRAM/DDR/DDR2 controller is equipped
  29 */
  30#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
  31        defined(CONFIG_AP1000) || defined(CONFIG_ML2)
  32#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM   /* IBM SDRAM controller */
  33#endif
  34
  35#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
  36    defined(CONFIG_440EP) || defined(CONFIG_440GR)
  37#define CONFIG_SDRAM_PPC4xx_IBM_DDR     /* IBM DDR controller */
  38#endif
  39
  40#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  41#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
  42#endif
  43
  44#if defined(CONFIG_405EX) || \
  45    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  46    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  47    defined(CONFIG_460SX)
  48#define CONFIG_SDRAM_PPC4xx_IBM_DDR2    /* IBM DDR(2) controller */
  49#endif
  50
  51#if defined(CONFIG_440EP) || defined(CONFIG_440GR) ||   \
  52    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  53    defined(CONFIG_405EZ) || defined(CONFIG_405EX) ||   \
  54    defined(CONFIG_460EX) || defined(CONFIG_460GT)
  55#define CONFIG_NAND_NDFC
  56#endif
  57
  58/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
  59#if defined(CONFIG_405EX) || \
  60    defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  61    defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  62    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  63    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
  64    defined(CONFIG_460SX)
  65
  66#define PLB_ARBITER_BASE                0x80
  67
  68#define plb0_revid                      (PLB_ARBITER_BASE + 0x00)
  69#define plb0_acr                        (PLB_ARBITER_BASE + 0x01)
  70#define plb0_acr_ppm_mask               0xF0000000
  71#define plb0_acr_ppm_fixed              0x00000000
  72#define plb0_acr_ppm_fair               0xD0000000
  73#define plb0_acr_hbu_mask               0x08000000
  74#define plb0_acr_hbu_disabled           0x00000000
  75#define plb0_acr_hbu_enabled            0x08000000
  76#define plb0_acr_rdp_mask               0x06000000
  77#define plb0_acr_rdp_disabled           0x00000000
  78#define plb0_acr_rdp_2deep              0x02000000
  79#define plb0_acr_rdp_3deep              0x04000000
  80#define plb0_acr_rdp_4deep              0x06000000
  81#define plb0_acr_wrp_mask               0x01000000
  82#define plb0_acr_wrp_disabled           0x00000000
  83#define plb0_acr_wrp_2deep              0x01000000
  84
  85#define plb0_besrl                      (PLB_ARBITER_BASE + 0x02)
  86#define plb0_besrh                      (PLB_ARBITER_BASE + 0x03)
  87#define plb0_bearl                      (PLB_ARBITER_BASE + 0x04)
  88#define plb0_bearh                      (PLB_ARBITER_BASE + 0x05)
  89#define plb0_ccr                        (PLB_ARBITER_BASE + 0x08)
  90
  91#define plb1_acr                        (PLB_ARBITER_BASE + 0x09)
  92#define plb1_acr_ppm_mask               0xF0000000
  93#define plb1_acr_ppm_fixed              0x00000000
  94#define plb1_acr_ppm_fair               0xD0000000
  95#define plb1_acr_hbu_mask               0x08000000
  96#define plb1_acr_hbu_disabled           0x00000000
  97#define plb1_acr_hbu_enabled            0x08000000
  98#define plb1_acr_rdp_mask               0x06000000
  99#define plb1_acr_rdp_disabled           0x00000000
 100#define plb1_acr_rdp_2deep              0x02000000
 101#define plb1_acr_rdp_3deep              0x04000000
 102#define plb1_acr_rdp_4deep              0x06000000
 103#define plb1_acr_wrp_mask               0x01000000
 104#define plb1_acr_wrp_disabled           0x00000000
 105#define plb1_acr_wrp_2deep              0x01000000
 106
 107#define plb1_besrl                      (PLB_ARBITER_BASE + 0x0A)
 108#define plb1_besrh                      (PLB_ARBITER_BASE + 0x0B)
 109#define plb1_bearl                      (PLB_ARBITER_BASE + 0x0C)
 110#define plb1_bearh                      (PLB_ARBITER_BASE + 0x0D)
 111
 112#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
 113
 114#if defined(CONFIG_440)
 115/*
 116 * Enable long long (%ll ...) printf format on 440 PPC's since most of
 117 * them support 36bit physical addressing
 118 */
 119#define CONFIG_SYS_64BIT_VSPRINTF
 120#define CONFIG_SYS_64BIT_STRTOUL
 121#include <ppc440.h>
 122#else
 123#include <ppc405.h>
 124#endif
 125
 126#include <asm/ppc4xx-sdram.h>
 127#include <asm/ppc4xx-ebc.h>
 128#if !defined(CONFIG_XILINX_440)
 129#include <asm/ppc4xx-uic.h>
 130#endif
 131
 132/*
 133 * Macro for generating register field mnemonics
 134 */
 135#define PPC_REG_BITS            32
 136#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
 137
 138/*
 139 * Elide casts when assembling register mnemonics
 140 */
 141#ifndef __ASSEMBLY__
 142#define static_cast(type, val)  (type)(val)
 143#else
 144#define static_cast(type, val)  (val)
 145#endif
 146
 147/*
 148 * Common stuff for 4xx (405 and 440)
 149 */
 150
 151#define EXC_OFF_SYS_RESET       0x0100  /* System reset                         */
 152#define _START_OFFSET           (EXC_OFF_SYS_RESET + 0x2000)
 153
 154#define RESET_VECTOR    0xfffffffc
 155#define CACHELINE_MASK  (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
 156                                                     line aligned data. */
 157
 158#define CPR0_DCR_BASE   0x0C
 159#define cprcfga         (CPR0_DCR_BASE+0x0)
 160#define cprcfgd         (CPR0_DCR_BASE+0x1)
 161
 162#define SDR_DCR_BASE    0x0E
 163#define sdrcfga         (SDR_DCR_BASE+0x0)
 164#define sdrcfgd         (SDR_DCR_BASE+0x1)
 165
 166#define SDRAM_DCR_BASE  0x10
 167#define memcfga         (SDRAM_DCR_BASE+0x0)
 168#define memcfgd         (SDRAM_DCR_BASE+0x1)
 169
 170#define EBC_DCR_BASE    0x12
 171#define ebccfga         (EBC_DCR_BASE+0x0)
 172#define ebccfgd         (EBC_DCR_BASE+0x1)
 173
 174/*
 175 * Macros for indirect DCR access
 176 */
 177#define mtcpr(reg, d)   do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
 178#define mfcpr(reg, d)   do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
 179
 180#define mtebc(reg, d)   do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
 181#define mfebc(reg, d)   do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
 182
 183#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
 184#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
 185
 186#define mtsdr(reg, d)   do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
 187#define mfsdr(reg, d)   do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
 188
 189#ifndef __ASSEMBLY__
 190
 191typedef struct
 192{
 193        unsigned long freqDDR;
 194        unsigned long freqEBC;
 195        unsigned long freqOPB;
 196        unsigned long freqPCI;
 197        unsigned long freqPLB;
 198        unsigned long freqTmrClk;
 199        unsigned long freqUART;
 200        unsigned long freqProcessor;
 201        unsigned long freqVCOHz;
 202        unsigned long freqVCOMhz;       /* in MHz                          */
 203        unsigned long pciClkSync;       /* PCI clock is synchronous        */
 204        unsigned long pciIntArbEn;      /* Internal PCI arbiter is enabled */
 205        unsigned long pllExtBusDiv;
 206        unsigned long pllFbkDiv;
 207        unsigned long pllFwdDiv;
 208        unsigned long pllFwdDivA;
 209        unsigned long pllFwdDivB;
 210        unsigned long pllOpbDiv;
 211        unsigned long pllPciDiv;
 212        unsigned long pllPlbDiv;
 213} PPC4xx_SYS_INFO;
 214
 215static inline u32 get_mcsr(void)
 216{
 217        u32 val;
 218
 219        asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
 220        return val;
 221}
 222
 223static inline void set_mcsr(u32 val)
 224{
 225        asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 226}
 227
 228#endif  /* __ASSEMBLY__ */
 229
 230/* for multi-cpu support */
 231#define NA_OR_UNKNOWN_CPU       -1
 232
 233#endif  /* __PPC4XX_H__ */
 234