LXR uboot/include/s3c24x0.h

   1/*
   2 * (C) Copyright 2003
   3 * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/************************************************
  25 * NAME     : s3c24x0.h
  26 * Version  : 31.3.2003
  27 *
  28 * common stuff for SAMSUNG S3C24X0 SoC
  29 ************************************************/
  30
  31#ifndef __S3C24X0_H__
  32#define __S3C24X0_H__
  33
  34typedef volatile u8     S3C24X0_REG8;
  35typedef volatile u16    S3C24X0_REG16;
  36typedef volatile u32    S3C24X0_REG32;
  37
  38/* Memory controller (see manual chapter 5) */
  39typedef struct {
  40        S3C24X0_REG32   BWSCON;
  41        S3C24X0_REG32   BANKCON[8];
  42        S3C24X0_REG32   REFRESH;
  43        S3C24X0_REG32   BANKSIZE;
  44        S3C24X0_REG32   MRSRB6;
  45        S3C24X0_REG32   MRSRB7;
  46} /*__attribute__((__packed__))*/ S3C24X0_MEMCTL;
  47
  48
  49/* USB HOST (see manual chapter 12) */
  50typedef struct {
  51        S3C24X0_REG32   HcRevision;
  52        S3C24X0_REG32   HcControl;
  53        S3C24X0_REG32   HcCommonStatus;
  54        S3C24X0_REG32   HcInterruptStatus;
  55        S3C24X0_REG32   HcInterruptEnable;
  56        S3C24X0_REG32   HcInterruptDisable;
  57        S3C24X0_REG32   HcHCCA;
  58        S3C24X0_REG32   HcPeriodCuttendED;
  59        S3C24X0_REG32   HcControlHeadED;
  60        S3C24X0_REG32   HcControlCurrentED;
  61        S3C24X0_REG32   HcBulkHeadED;
  62        S3C24X0_REG32   HcBuldCurrentED;
  63        S3C24X0_REG32   HcDoneHead;
  64        S3C24X0_REG32   HcRmInterval;
  65        S3C24X0_REG32   HcFmRemaining;
  66        S3C24X0_REG32   HcFmNumber;
  67        S3C24X0_REG32   HcPeriodicStart;
  68        S3C24X0_REG32   HcLSThreshold;
  69        S3C24X0_REG32   HcRhDescriptorA;
  70        S3C24X0_REG32   HcRhDescriptorB;
  71        S3C24X0_REG32   HcRhStatus;
  72        S3C24X0_REG32   HcRhPortStatus1;
  73        S3C24X0_REG32   HcRhPortStatus2;
  74} /*__attribute__((__packed__))*/ S3C24X0_USB_HOST;
  75
  76
  77/* INTERRUPT (see manual chapter 14) */
  78typedef struct {
  79        S3C24X0_REG32   SRCPND;
  80        S3C24X0_REG32   INTMOD;
  81        S3C24X0_REG32   INTMSK;
  82        S3C24X0_REG32   PRIORITY;
  83        S3C24X0_REG32   INTPND;
  84        S3C24X0_REG32   INTOFFSET;
  85#ifdef CONFIG_S3C2410
  86        S3C24X0_REG32   SUBSRCPND;
  87        S3C24X0_REG32   INTSUBMSK;
  88#endif
  89} /*__attribute__((__packed__))*/ S3C24X0_INTERRUPT;
  90
  91
  92/* DMAS (see manual chapter 8) */
  93typedef struct {
  94        S3C24X0_REG32   DISRC;
  95#ifdef CONFIG_S3C2410
  96        S3C24X0_REG32   DISRCC;
  97#endif
  98        S3C24X0_REG32   DIDST;
  99#ifdef CONFIG_S3C2410
 100        S3C24X0_REG32   DIDSTC;
 101#endif
 102        S3C24X0_REG32   DCON;
 103        S3C24X0_REG32   DSTAT;
 104        S3C24X0_REG32   DCSRC;
 105        S3C24X0_REG32   DCDST;
 106        S3C24X0_REG32   DMASKTRIG;
 107#ifdef CONFIG_S3C2400
 108        S3C24X0_REG32   res[1];
 109#endif
 110#ifdef CONFIG_S3C2410
 111        S3C24X0_REG32   res[7];
 112#endif
 113} /*__attribute__((__packed__))*/ S3C24X0_DMA;
 114
 115typedef struct {
 116        S3C24X0_DMA     dma[4];
 117} /*__attribute__((__packed__))*/ S3C24X0_DMAS;
 118
 119
 120/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
 121/*                          (see S3C2410 manual chapter 7) */
 122typedef struct {
 123        S3C24X0_REG32   LOCKTIME;
 124        S3C24X0_REG32   MPLLCON;
 125        S3C24X0_REG32   UPLLCON;
 126        S3C24X0_REG32   CLKCON;
 127        S3C24X0_REG32   CLKSLOW;
 128        S3C24X0_REG32   CLKDIVN;
 129} /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
 130
 131
 132/* LCD CONTROLLER (see manual chapter 15) */
 133typedef struct {
 134        S3C24X0_REG32   LCDCON1;
 135        S3C24X0_REG32   LCDCON2;
 136        S3C24X0_REG32   LCDCON3;
 137        S3C24X0_REG32   LCDCON4;
 138        S3C24X0_REG32   LCDCON5;
 139        S3C24X0_REG32   LCDSADDR1;
 140        S3C24X0_REG32   LCDSADDR2;
 141        S3C24X0_REG32   LCDSADDR3;
 142        S3C24X0_REG32   REDLUT;
 143        S3C24X0_REG32   GREENLUT;
 144        S3C24X0_REG32   BLUELUT;
 145        S3C24X0_REG32   res[8];
 146        S3C24X0_REG32   DITHMODE;
 147        S3C24X0_REG32   TPAL;
 148#ifdef CONFIG_S3C2410
 149        S3C24X0_REG32   LCDINTPND;
 150        S3C24X0_REG32   LCDSRCPND;
 151        S3C24X0_REG32   LCDINTMSK;
 152        S3C24X0_REG32   LPCSEL;
 153#endif
 154} /*__attribute__((__packed__))*/ S3C24X0_LCD;
 155
 156
 157/* NAND FLASH (see S3C2410 manual chapter 6) */
 158typedef struct {
 159        S3C24X0_REG32   NFCONF;
 160        S3C24X0_REG32   NFCMD;
 161        S3C24X0_REG32   NFADDR;
 162        S3C24X0_REG32   NFDATA;
 163        S3C24X0_REG32   NFSTAT;
 164        S3C24X0_REG32   NFECC;
 165} /*__attribute__((__packed__))*/ S3C2410_NAND;
 166
 167
 168/* UART (see manual chapter 11) */
 169typedef struct {
 170        S3C24X0_REG32   ULCON;
 171        S3C24X0_REG32   UCON;
 172        S3C24X0_REG32   UFCON;
 173        S3C24X0_REG32   UMCON;
 174        S3C24X0_REG32   UTRSTAT;
 175        S3C24X0_REG32   UERSTAT;
 176        S3C24X0_REG32   UFSTAT;
 177        S3C24X0_REG32   UMSTAT;
 178#ifdef __BIG_ENDIAN
 179        S3C24X0_REG8    res1[3];
 180        S3C24X0_REG8    UTXH;
 181        S3C24X0_REG8    res2[3];
 182        S3C24X0_REG8    URXH;
 183#else /* Little Endian */
 184        S3C24X0_REG8    UTXH;
 185        S3C24X0_REG8    res1[3];
 186        S3C24X0_REG8    URXH;
 187        S3C24X0_REG8    res2[3];
 188#endif
 189        S3C24X0_REG32   UBRDIV;
 190} /*__attribute__((__packed__))*/ S3C24X0_UART;
 191
 192
 193/* PWM TIMER (see manual chapter 10) */
 194typedef struct {
 195        S3C24X0_REG32   TCNTB;
 196        S3C24X0_REG32   TCMPB;
 197        S3C24X0_REG32   TCNTO;
 198} /*__attribute__((__packed__))*/ S3C24X0_TIMER;
 199
 200typedef struct {
 201        S3C24X0_REG32   TCFG0;
 202        S3C24X0_REG32   TCFG1;
 203        S3C24X0_REG32   TCON;
 204        S3C24X0_TIMER   ch[4];
 205        S3C24X0_REG32   TCNTB4;
 206        S3C24X0_REG32   TCNTO4;
 207} /*__attribute__((__packed__))*/ S3C24X0_TIMERS;
 208
 209
 210/* USB DEVICE (see manual chapter 13) */
 211typedef struct {
 212#ifdef __BIG_ENDIAN
 213        S3C24X0_REG8    res[3];
 214        S3C24X0_REG8    EP_FIFO_REG;
 215#else /*  little endian */
 216        S3C24X0_REG8    EP_FIFO_REG;
 217        S3C24X0_REG8    res[3];
 218#endif
 219} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_FIFOS;
 220
 221typedef struct {
 222#ifdef __BIG_ENDIAN
 223        S3C24X0_REG8    res1[3];
 224        S3C24X0_REG8    EP_DMA_CON;
 225        S3C24X0_REG8    res2[3];
 226        S3C24X0_REG8    EP_DMA_UNIT;
 227        S3C24X0_REG8    res3[3];
 228        S3C24X0_REG8    EP_DMA_FIFO;
 229        S3C24X0_REG8    res4[3];
 230        S3C24X0_REG8    EP_DMA_TTC_L;
 231        S3C24X0_REG8    res5[3];
 232        S3C24X0_REG8    EP_DMA_TTC_M;
 233        S3C24X0_REG8    res6[3];
 234        S3C24X0_REG8    EP_DMA_TTC_H;
 235#else /*  little endian */
 236        S3C24X0_REG8    EP_DMA_CON;
 237        S3C24X0_REG8    res1[3];
 238        S3C24X0_REG8    EP_DMA_UNIT;
 239        S3C24X0_REG8    res2[3];
 240        S3C24X0_REG8    EP_DMA_FIFO;
 241        S3C24X0_REG8    res3[3];
 242        S3C24X0_REG8    EP_DMA_TTC_L;
 243        S3C24X0_REG8    res4[3];
 244        S3C24X0_REG8    EP_DMA_TTC_M;
 245        S3C24X0_REG8    res5[3];
 246        S3C24X0_REG8    EP_DMA_TTC_H;
 247        S3C24X0_REG8    res6[3];
 248#endif
 249} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS;
 250
 251typedef struct {
 252#ifdef __BIG_ENDIAN
 253        S3C24X0_REG8    res1[3];
 254        S3C24X0_REG8    FUNC_ADDR_REG;
 255        S3C24X0_REG8    res2[3];
 256        S3C24X0_REG8    PWR_REG;
 257        S3C24X0_REG8    res3[3];
 258        S3C24X0_REG8    EP_INT_REG;
 259        S3C24X0_REG8    res4[15];
 260        S3C24X0_REG8    USB_INT_REG;
 261        S3C24X0_REG8    res5[3];
 262        S3C24X0_REG8    EP_INT_EN_REG;
 263        S3C24X0_REG8    res6[15];
 264        S3C24X0_REG8    USB_INT_EN_REG;
 265        S3C24X0_REG8    res7[3];
 266        S3C24X0_REG8    FRAME_NUM1_REG;
 267        S3C24X0_REG8    res8[3];
 268        S3C24X0_REG8    FRAME_NUM2_REG;
 269        S3C24X0_REG8    res9[3];
 270        S3C24X0_REG8    INDEX_REG;
 271        S3C24X0_REG8    res10[7];
 272        S3C24X0_REG8    MAXP_REG;
 273        S3C24X0_REG8    res11[3];
 274        S3C24X0_REG8    EP0_CSR_IN_CSR1_REG;
 275        S3C24X0_REG8    res12[3];
 276        S3C24X0_REG8    IN_CSR2_REG;
 277        S3C24X0_REG8    res13[7];
 278        S3C24X0_REG8    OUT_CSR1_REG;
 279        S3C24X0_REG8    res14[3];
 280        S3C24X0_REG8    OUT_CSR2_REG;
 281        S3C24X0_REG8    res15[3];
 282        S3C24X0_REG8    OUT_FIFO_CNT1_REG;
 283        S3C24X0_REG8    res16[3];
 284        S3C24X0_REG8    OUT_FIFO_CNT2_REG;
 285#else /*  little endian */
 286        S3C24X0_REG8    FUNC_ADDR_REG;
 287        S3C24X0_REG8    res1[3];
 288        S3C24X0_REG8    PWR_REG;
 289        S3C24X0_REG8    res2[3];
 290        S3C24X0_REG8    EP_INT_REG;
 291        S3C24X0_REG8    res3[15];
 292        S3C24X0_REG8    USB_INT_REG;
 293        S3C24X0_REG8    res4[3];
 294        S3C24X0_REG8    EP_INT_EN_REG;
 295        S3C24X0_REG8    res5[15];
 296        S3C24X0_REG8    USB_INT_EN_REG;
 297        S3C24X0_REG8    res6[3];
 298        S3C24X0_REG8    FRAME_NUM1_REG;
 299        S3C24X0_REG8    res7[3];
 300        S3C24X0_REG8    FRAME_NUM2_REG;
 301        S3C24X0_REG8    res8[3];
 302        S3C24X0_REG8    INDEX_REG;
 303        S3C24X0_REG8    res9[7];
 304        S3C24X0_REG8    MAXP_REG;
 305        S3C24X0_REG8    res10[7];
 306        S3C24X0_REG8    EP0_CSR_IN_CSR1_REG;
 307        S3C24X0_REG8    res11[3];
 308        S3C24X0_REG8    IN_CSR2_REG;
 309        S3C24X0_REG8    res12[3];
 310        S3C24X0_REG8    OUT_CSR1_REG;
 311        S3C24X0_REG8    res13[7];
 312        S3C24X0_REG8    OUT_CSR2_REG;
 313        S3C24X0_REG8    res14[3];
 314        S3C24X0_REG8    OUT_FIFO_CNT1_REG;
 315        S3C24X0_REG8    res15[3];
 316        S3C24X0_REG8    OUT_FIFO_CNT2_REG;
 317        S3C24X0_REG8    res16[3];
 318#endif /*  __BIG_ENDIAN */
 319        S3C24X0_USB_DEV_FIFOS   fifo[5];
 320        S3C24X0_USB_DEV_DMAS    dma[5];
 321} /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
 322
 323
 324/* WATCH DOG TIMER (see manual chapter 18) */
 325typedef struct {
 326        S3C24X0_REG32   WTCON;
 327        S3C24X0_REG32   WTDAT;
 328        S3C24X0_REG32   WTCNT;
 329} /*__attribute__((__packed__))*/ S3C24X0_WATCHDOG;
 330
 331
 332/* IIC (see manual chapter 20) */
 333typedef struct {
 334        S3C24X0_REG32   IICCON;
 335        S3C24X0_REG32   IICSTAT;
 336        S3C24X0_REG32   IICADD;
 337        S3C24X0_REG32   IICDS;
 338} /*__attribute__((__packed__))*/ S3C24X0_I2C;
 339
 340
 341/* IIS (see manual chapter 21) */
 342typedef struct {
 343#ifdef __BIG_ENDIAN
 344        S3C24X0_REG16   res1;
 345        S3C24X0_REG16   IISCON;
 346        S3C24X0_REG16   res2;
 347        S3C24X0_REG16   IISMOD;
 348        S3C24X0_REG16   res3;
 349        S3C24X0_REG16   IISPSR;
 350        S3C24X0_REG16   res4;
 351        S3C24X0_REG16   IISFCON;
 352        S3C24X0_REG16   res5;
 353        S3C24X0_REG16   IISFIFO;
 354#else /*  little endian */
 355        S3C24X0_REG16   IISCON;
 356        S3C24X0_REG16   res1;
 357        S3C24X0_REG16   IISMOD;
 358        S3C24X0_REG16   res2;
 359        S3C24X0_REG16   IISPSR;
 360        S3C24X0_REG16   res3;
 361        S3C24X0_REG16   IISFCON;
 362        S3C24X0_REG16   res4;
 363        S3C24X0_REG16   IISFIFO;
 364        S3C24X0_REG16   res5;
 365#endif
 366} /*__attribute__((__packed__))*/ S3C24X0_I2S;
 367
 368
 369/* I/O PORT (see manual chapter 9) */
 370typedef struct {
 371#ifdef CONFIG_S3C2400
 372        S3C24X0_REG32   PACON;
 373        S3C24X0_REG32   PADAT;
 374
 375        S3C24X0_REG32   PBCON;
 376        S3C24X0_REG32   PBDAT;
 377        S3C24X0_REG32   PBUP;
 378
 379        S3C24X0_REG32   PCCON;
 380        S3C24X0_REG32   PCDAT;
 381        S3C24X0_REG32   PCUP;
 382
 383        S3C24X0_REG32   PDCON;
 384        S3C24X0_REG32   PDDAT;
 385        S3C24X0_REG32   PDUP;
 386
 387        S3C24X0_REG32   PECON;
 388        S3C24X0_REG32   PEDAT;
 389        S3C24X0_REG32   PEUP;
 390
 391        S3C24X0_REG32   PFCON;
 392        S3C24X0_REG32   PFDAT;
 393        S3C24X0_REG32   PFUP;
 394
 395        S3C24X0_REG32   PGCON;
 396        S3C24X0_REG32   PGDAT;
 397        S3C24X0_REG32   PGUP;
 398
 399        S3C24X0_REG32   OPENCR;
 400
 401        S3C24X0_REG32   MISCCR;
 402        S3C24X0_REG32   EXTINT;
 403#endif
 404#ifdef CONFIG_S3C2410
 405        S3C24X0_REG32   GPACON;
 406        S3C24X0_REG32   GPADAT;
 407        S3C24X0_REG32   res1[2];
 408        S3C24X0_REG32   GPBCON;
 409        S3C24X0_REG32   GPBDAT;
 410        S3C24X0_REG32   GPBUP;
 411        S3C24X0_REG32   res2;
 412        S3C24X0_REG32   GPCCON;
 413        S3C24X0_REG32   GPCDAT;
 414        S3C24X0_REG32   GPCUP;
 415        S3C24X0_REG32   res3;
 416        S3C24X0_REG32   GPDCON;
 417        S3C24X0_REG32   GPDDAT;
 418        S3C24X0_REG32   GPDUP;
 419        S3C24X0_REG32   res4;
 420        S3C24X0_REG32   GPECON;
 421        S3C24X0_REG32   GPEDAT;
 422        S3C24X0_REG32   GPEUP;
 423        S3C24X0_REG32   res5;
 424        S3C24X0_REG32   GPFCON;
 425        S3C24X0_REG32   GPFDAT;
 426        S3C24X0_REG32   GPFUP;
 427        S3C24X0_REG32   res6;
 428        S3C24X0_REG32   GPGCON;
 429        S3C24X0_REG32   GPGDAT;
 430        S3C24X0_REG32   GPGUP;
 431        S3C24X0_REG32   res7;
 432        S3C24X0_REG32   GPHCON;
 433        S3C24X0_REG32   GPHDAT;
 434        S3C24X0_REG32   GPHUP;
 435        S3C24X0_REG32   res8;
 436
 437        S3C24X0_REG32   MISCCR;
 438        S3C24X0_REG32   DCLKCON;
 439        S3C24X0_REG32   EXTINT0;
 440        S3C24X0_REG32   EXTINT1;
 441        S3C24X0_REG32   EXTINT2;
 442        S3C24X0_REG32   EINTFLT0;
 443        S3C24X0_REG32   EINTFLT1;
 444        S3C24X0_REG32   EINTFLT2;
 445        S3C24X0_REG32   EINTFLT3;
 446        S3C24X0_REG32   EINTMASK;
 447        S3C24X0_REG32   EINTPEND;
 448        S3C24X0_REG32   GSTATUS0;
 449        S3C24X0_REG32   GSTATUS1;
 450        S3C24X0_REG32   GSTATUS2;
 451        S3C24X0_REG32   GSTATUS3;
 452        S3C24X0_REG32   GSTATUS4;
 453#endif
 454} /*__attribute__((__packed__))*/ S3C24X0_GPIO;
 455
 456
 457/* RTC (see manual chapter 17) */
 458typedef struct {
 459#ifdef __BIG_ENDIAN
 460        S3C24X0_REG8    res1[67];
 461        S3C24X0_REG8    RTCCON;
 462        S3C24X0_REG8    res2[3];
 463        S3C24X0_REG8    TICNT;
 464        S3C24X0_REG8    res3[11];
 465        S3C24X0_REG8    RTCALM;
 466        S3C24X0_REG8    res4[3];
 467        S3C24X0_REG8    ALMSEC;
 468        S3C24X0_REG8    res5[3];
 469        S3C24X0_REG8    ALMMIN;
 470        S3C24X0_REG8    res6[3];
 471        S3C24X0_REG8    ALMHOUR;
 472        S3C24X0_REG8    res7[3];
 473        S3C24X0_REG8    ALMDATE;
 474        S3C24X0_REG8    res8[3];
 475        S3C24X0_REG8    ALMMON;
 476        S3C24X0_REG8    res9[3];
 477        S3C24X0_REG8    ALMYEAR;
 478        S3C24X0_REG8    res10[3];
 479        S3C24X0_REG8    RTCRST;
 480        S3C24X0_REG8    res11[3];
 481        S3C24X0_REG8    BCDSEC;
 482        S3C24X0_REG8    res12[3];
 483        S3C24X0_REG8    BCDMIN;
 484        S3C24X0_REG8    res13[3];
 485        S3C24X0_REG8    BCDHOUR;
 486        S3C24X0_REG8    res14[3];
 487        S3C24X0_REG8    BCDDATE;
 488        S3C24X0_REG8    res15[3];
 489        S3C24X0_REG8    BCDDAY;
 490        S3C24X0_REG8    res16[3];
 491        S3C24X0_REG8    BCDMON;
 492        S3C24X0_REG8    res17[3];
 493        S3C24X0_REG8    BCDYEAR;
 494#else /*  little endian */
 495        S3C24X0_REG8    res0[64];
 496        S3C24X0_REG8    RTCCON;
 497        S3C24X0_REG8    res1[3];
 498        S3C24X0_REG8    TICNT;
 499        S3C24X0_REG8    res2[11];
 500        S3C24X0_REG8    RTCALM;
 501        S3C24X0_REG8    res3[3];
 502        S3C24X0_REG8    ALMSEC;
 503        S3C24X0_REG8    res4[3];
 504        S3C24X0_REG8    ALMMIN;
 505        S3C24X0_REG8    res5[3];
 506        S3C24X0_REG8    ALMHOUR;
 507        S3C24X0_REG8    res6[3];
 508        S3C24X0_REG8    ALMDATE;
 509        S3C24X0_REG8    res7[3];
 510        S3C24X0_REG8    ALMMON;
 511        S3C24X0_REG8    res8[3];
 512        S3C24X0_REG8    ALMYEAR;
 513        S3C24X0_REG8    res9[3];
 514        S3C24X0_REG8    RTCRST;
 515        S3C24X0_REG8    res10[3];
 516        S3C24X0_REG8    BCDSEC;
 517        S3C24X0_REG8    res11[3];
 518        S3C24X0_REG8    BCDMIN;
 519        S3C24X0_REG8    res12[3];
 520        S3C24X0_REG8    BCDHOUR;
 521        S3C24X0_REG8    res13[3];
 522        S3C24X0_REG8    BCDDATE;
 523        S3C24X0_REG8    res14[3];
 524        S3C24X0_REG8    BCDDAY;
 525        S3C24X0_REG8    res15[3];
 526        S3C24X0_REG8    BCDMON;
 527        S3C24X0_REG8    res16[3];
 528        S3C24X0_REG8    BCDYEAR;
 529        S3C24X0_REG8    res17[3];
 530#endif
 531} /*__attribute__((__packed__))*/ S3C24X0_RTC;
 532
 533
 534/* ADC (see manual chapter 16) */
 535typedef struct {
 536        S3C24X0_REG32   ADCCON;
 537        S3C24X0_REG32   ADCDAT;
 538} /*__attribute__((__packed__))*/ S3C2400_ADC;
 539
 540
 541/* ADC (see manual chapter 16) */
 542typedef struct {
 543        S3C24X0_REG32   ADCCON;
 544        S3C24X0_REG32   ADCTSC;
 545        S3C24X0_REG32   ADCDLY;
 546        S3C24X0_REG32   ADCDAT0;
 547        S3C24X0_REG32   ADCDAT1;
 548} /*__attribute__((__packed__))*/ S3C2410_ADC;
 549
 550
 551/* SPI (see manual chapter 22) */
 552typedef struct {
 553        S3C24X0_REG8    SPCON;
 554        S3C24X0_REG8    res1[3];
 555        S3C24X0_REG8    SPSTA;
 556        S3C24X0_REG8    res2[3];
 557        S3C24X0_REG8    SPPIN;
 558        S3C24X0_REG8    res3[3];
 559        S3C24X0_REG8    SPPRE;
 560        S3C24X0_REG8    res4[3];
 561        S3C24X0_REG8    SPTDAT;
 562        S3C24X0_REG8    res5[3];
 563        S3C24X0_REG8    SPRDAT;
 564        S3C24X0_REG8    res6[3];
 565        S3C24X0_REG8    res7[16];
 566} /*__attribute__((__packed__))*/ S3C24X0_SPI_CHANNEL;
 567
 568typedef struct {
 569        S3C24X0_SPI_CHANNEL     ch[S3C24X0_SPI_CHANNELS];
 570} /*__attribute__((__packed__))*/ S3C24X0_SPI;
 571
 572
 573/* MMC INTERFACE (see S3C2400 manual chapter 19) */
 574typedef struct {
 575#ifdef __BIG_ENDIAN
 576        S3C24X0_REG8    res1[3];
 577        S3C24X0_REG8    MMCON;
 578        S3C24X0_REG8    res2[3];
 579        S3C24X0_REG8    MMCRR;
 580        S3C24X0_REG8    res3[3];
 581        S3C24X0_REG8    MMFCON;
 582        S3C24X0_REG8    res4[3];
 583        S3C24X0_REG8    MMSTA;
 584        S3C24X0_REG16   res5;
 585        S3C24X0_REG16   MMFSTA;
 586        S3C24X0_REG8    res6[3];
 587        S3C24X0_REG8    MMPRE;
 588        S3C24X0_REG16   res7;
 589        S3C24X0_REG16   MMLEN;
 590        S3C24X0_REG8    res8[3];
 591        S3C24X0_REG8    MMCR7;
 592        S3C24X0_REG32   MMRSP[4];
 593        S3C24X0_REG8    res9[3];
 594        S3C24X0_REG8    MMCMD0;
 595        S3C24X0_REG32   MMCMD1;
 596        S3C24X0_REG16   res10;
 597        S3C24X0_REG16   MMCR16;
 598        S3C24X0_REG8    res11[3];
 599        S3C24X0_REG8    MMDAT;
 600#else
 601        S3C24X0_REG8    MMCON;
 602        S3C24X0_REG8    res1[3];
 603        S3C24X0_REG8    MMCRR;
 604        S3C24X0_REG8    res2[3];
 605        S3C24X0_REG8    MMFCON;
 606        S3C24X0_REG8    res3[3];
 607        S3C24X0_REG8    MMSTA;
 608        S3C24X0_REG8    res4[3];
 609        S3C24X0_REG16   MMFSTA;
 610        S3C24X0_REG16   res5;
 611        S3C24X0_REG8    MMPRE;
 612        S3C24X0_REG8    res6[3];
 613        S3C24X0_REG16   MMLEN;
 614        S3C24X0_REG16   res7;
 615        S3C24X0_REG8    MMCR7;
 616        S3C24X0_REG8    res8[3];
 617        S3C24X0_REG32   MMRSP[4];
 618        S3C24X0_REG8    MMCMD0;
 619        S3C24X0_REG8    res9[3];
 620        S3C24X0_REG32   MMCMD1;
 621        S3C24X0_REG16   MMCR16;
 622        S3C24X0_REG16   res10;
 623        S3C24X0_REG8    MMDAT;
 624        S3C24X0_REG8    res11[3];
 625#endif
 626} /*__attribute__((__packed__))*/ S3C2400_MMC;
 627
 628
 629/* SD INTERFACE (see S3C2410 manual chapter 19) */
 630typedef struct {
 631        S3C24X0_REG32   SDICON;
 632        S3C24X0_REG32   SDIPRE;
 633        S3C24X0_REG32   SDICARG;
 634        S3C24X0_REG32   SDICCON;
 635        S3C24X0_REG32   SDICSTA;
 636        S3C24X0_REG32   SDIRSP0;
 637        S3C24X0_REG32   SDIRSP1;
 638        S3C24X0_REG32   SDIRSP2;
 639        S3C24X0_REG32   SDIRSP3;
 640        S3C24X0_REG32   SDIDTIMER;
 641        S3C24X0_REG32   SDIBSIZE;
 642        S3C24X0_REG32   SDIDCON;
 643        S3C24X0_REG32   SDIDCNT;
 644        S3C24X0_REG32   SDIDSTA;
 645        S3C24X0_REG32   SDIFSTA;
 646#ifdef __BIG_ENDIAN
 647        S3C24X0_REG8    res[3];
 648        S3C24X0_REG8    SDIDAT;
 649#else
 650        S3C24X0_REG8    SDIDAT;
 651        S3C24X0_REG8    res[3];
 652#endif
 653        S3C24X0_REG32   SDIIMSK;
 654} /*__attribute__((__packed__))*/ S3C2410_SDI;
 655
 656
 657#if 0
 658/* Memory control */
 659#define rBWSCON                 (*(volatile unsigned *)0x48000000)
 660#define rBANKCON0               (*(volatile unsigned *)0x48000004)
 661#define rBANKCON1               (*(volatile unsigned *)0x48000008)
 662#define rBANKCON2               (*(volatile unsigned *)0x4800000C)
 663#define rBANKCON3               (*(volatile unsigned *)0x48000010)
 664#define rBANKCON4               (*(volatile unsigned *)0x48000014)
 665#define rBANKCON5               (*(volatile unsigned *)0x48000018)
 666#define rBANKCON6               (*(volatile unsigned *)0x4800001C)
 667#define rBANKCON7               (*(volatile unsigned *)0x48000020)
 668#define rREFRESH                (*(volatile unsigned *)0x48000024)
 669#define rBANKSIZE               (*(volatile unsigned *)0x48000028)
 670#define rMRSRB6                 (*(volatile unsigned *)0x4800002C)
 671#define rMRSRB7                 (*(volatile unsigned *)0x48000030)
 672
 673
 674/* USB HOST */
 675#define rHcRevision             (*(volatile unsigned *)0x49000000)
 676#define rHcControl              (*(volatile unsigned *)0x49000004)
 677#define rHcCommonStatus         (*(volatile unsigned *)0x49000008)
 678#define rHcInterruptStatus      (*(volatile unsigned *)0x4900000C)
 679#define rHcInterruptEnable      (*(volatile unsigned *)0x49000010)
 680#define rHcInterruptDisable     (*(volatile unsigned *)0x49000014)
 681#define rHcHCCA                 (*(volatile unsigned *)0x49000018)
 682#define rHcPeriodCuttendED      (*(volatile unsigned *)0x4900001C)
 683#define rHcControlHeadED        (*(volatile unsigned *)0x49000020)
 684#define rHcControlCurrentED     (*(volatile unsigned *)0x49000024)
 685#define rHcBulkHeadED           (*(volatile unsigned *)0x49000028)
 686#define rHcBuldCurrentED        (*(volatile unsigned *)0x4900002C)
 687#define rHcDoneHead             (*(volatile unsigned *)0x49000030)
 688#define rHcRmInterval           (*(volatile unsigned *)0x49000034)
 689#define rHcFmRemaining          (*(volatile unsigned *)0x49000038)
 690#define rHcFmNumber             (*(volatile unsigned *)0x4900003C)
 691#define rHcPeriodicStart        (*(volatile unsigned *)0x49000040)
 692#define rHcLSThreshold          (*(volatile unsigned *)0x49000044)
 693#define rHcRhDescriptorA        (*(volatile unsigned *)0x49000048)
 694#define rHcRhDescriptorB        (*(volatile unsigned *)0x4900004C)
 695#define rHcRhStatus             (*(volatile unsigned *)0x49000050)
 696#define rHcRhPortStatus1        (*(volatile unsigned *)0x49000054)
 697#define rHcRhPortStatus2        (*(volatile unsigned *)0x49000058)
 698
 699
 700/* INTERRUPT */
 701#define rSRCPND                 (*(volatile unsigned *)0x4A000000)
 702#define rINTMOD                 (*(volatile unsigned *)0x4A000004)
 703#define rINTMSK                 (*(volatile unsigned *)0x4A000008)
 704#define rPRIORITY               (*(volatile unsigned *)0x4A00000C)
 705#define rINTPND                 (*(volatile unsigned *)0x4A000010)
 706#define rINTOFFSET              (*(volatile unsigned *)0x4A000014)
 707#define rSUBSRCPND              (*(volatile unsigned *)0x4A000018)
 708#define rINTSUBMSK              (*(volatile unsigned *)0x4A00001C)
 709
 710
 711/* DMA */
 712#define rDISRC0                 (*(volatile unsigned *)0x4B000000)
 713#define rDISRCC0                (*(volatile unsigned *)0x4B000004)
 714#define rDIDST0                 (*(volatile unsigned *)0x4B000008)
 715#define rDIDSTC0                (*(volatile unsigned *)0x4B00000C)
 716#define rDCON0                  (*(volatile unsigned *)0x4B000010)
 717#define rDSTAT0                 (*(volatile unsigned *)0x4B000014)
 718#define rDCSRC0                 (*(volatile unsigned *)0x4B000018)
 719#define rDCDST0                 (*(volatile unsigned *)0x4B00001C)
 720#define rDMASKTRIG0             (*(volatile unsigned *)0x4B000020)
 721#define rDISRC1                 (*(volatile unsigned *)0x4B000040)
 722#define rDISRCC1                (*(volatile unsigned *)0x4B000044)
 723#define rDIDST1                 (*(volatile unsigned *)0x4B000048)
 724#define rDIDSTC1                (*(volatile unsigned *)0x4B00004C)
 725#define rDCON1                  (*(volatile unsigned *)0x4B000050)
 726#define rDSTAT1                 (*(volatile unsigned *)0x4B000054)
 727#define rDCSRC1                 (*(volatile unsigned *)0x4B000058)
 728#define rDCDST1                 (*(volatile unsigned *)0x4B00005C)
 729#define rDMASKTRIG1             (*(volatile unsigned *)0x4B000060)
 730#define rDISRC2                 (*(volatile unsigned *)0x4B000080)
 731#define rDISRCC2                (*(volatile unsigned *)0x4B000084)
 732#define rDIDST2                 (*(volatile unsigned *)0x4B000088)
 733#define rDIDSTC2                (*(volatile unsigned *)0x4B00008C)
 734#define rDCON2                  (*(volatile unsigned *)0x4B000090)
 735#define rDSTAT2                 (*(volatile unsigned *)0x4B000094)
 736#define rDCSRC2                 (*(volatile unsigned *)0x4B000098)
 737#define rDCDST2                 (*(volatile unsigned *)0x4B00009C)
 738#define rDMASKTRIG2             (*(volatile unsigned *)0x4B0000A0)
 739#define rDISRC3                 (*(volatile unsigned *)0x4B0000C0)
 740#define rDISRCC3                (*(volatile unsigned *)0x4B0000C4)
 741#define rDIDST3                 (*(volatile unsigned *)0x4B0000C8)
 742#define rDIDSTC3                (*(volatile unsigned *)0x4B0000CC)
 743#define rDCON3                  (*(volatile unsigned *)0x4B0000D0)
 744#define rDSTAT3                 (*(volatile unsigned *)0x4B0000D4)
 745#define rDCSRC3                 (*(volatile unsigned *)0x4B0000D8)
 746#define rDCDST3                 (*(volatile unsigned *)0x4B0000DC)
 747#define rDMASKTRIG3             (*(volatile unsigned *)0x4B0000E0)
 748
 749
 750/* CLOCK & POWER MANAGEMENT */
 751#define rLOCKTIME               (*(volatile unsigned *)0x4C000000)
 752#define rMPLLCON                (*(volatile unsigned *)0x4C000004)
 753#define rUPLLCON                (*(volatile unsigned *)0x4C000008)
 754#define rCLKCON                 (*(volatile unsigned *)0x4C00000C)
 755#define rCLKSLOW                (*(volatile unsigned *)0x4C000010)
 756#define rCLKDIVN                (*(volatile unsigned *)0x4C000014)
 757
 758
 759/* LCD CONTROLLER */
 760#define rLCDCON1                (*(volatile unsigned *)0x4D000000)
 761#define rLCDCON2                (*(volatile unsigned *)0x4D000004)
 762#define rLCDCON3                (*(volatile unsigned *)0x4D000008)
 763#define rLCDCON4                (*(volatile unsigned *)0x4D00000C)
 764#define rLCDCON5                (*(volatile unsigned *)0x4D000010)
 765#define rLCDSADDR1              (*(volatile unsigned *)0x4D000014)
 766#define rLCDSADDR2              (*(volatile unsigned *)0x4D000018)
 767#define rLCDSADDR3              (*(volatile unsigned *)0x4D00001C)
 768#define rREDLUT                 (*(volatile unsigned *)0x4D000020)
 769#define rGREENLUT               (*(volatile unsigned *)0x4D000024)
 770#define rBLUELUT                (*(volatile unsigned *)0x4D000028)
 771#define rDITHMODE               (*(volatile unsigned *)0x4D00004C)
 772#define rTPAL                   (*(volatile unsigned *)0x4D000050)
 773#define rLCDINTPND              (*(volatile unsigned *)0x4D000054)
 774#define rLCDSRCPND              (*(volatile unsigned *)0x4D000058)
 775#define rLCDINTMSK              (*(volatile unsigned *)0x4D00005C)
 776
 777
 778/* NAND FLASH */
 779#define rNFCONF                 (*(volatile unsigned *)0x4E000000)
 780#define rNFCMD                  (*(volatile unsigned *)0x4E000004)
 781#define rNFADDR                 (*(volatile unsigned *)0x4E000008)
 782#define rNFDATA                 (*(volatile unsigned *)0x4E00000C)
 783#define rNFSTAT                 (*(volatile unsigned *)0x4E000010)
 784#define rNFECC                  (*(volatile unsigned *)0x4E000014)
 785
 786
 787/* UART */
 788#define rULCON0                 (*(volatile unsigned *)0x50000000)
 789#define rUCON0                  (*(volatile unsigned *)0x50000004)
 790#define rUFCON0                 (*(volatile unsigned *)0x50000008)
 791#define rUMCON0                 (*(volatile unsigned *)0x5000000C)
 792#define rUTRSTAT0               (*(volatile unsigned *)0x50000010)
 793#define rUERSTAT0               (*(volatile unsigned *)0x50000014)
 794#define rUFSTAT0                (*(volatile unsigned *)0x50000018)
 795#define rUMSTAT0                (*(volatile unsigned *)0x5000001C)
 796#define rUBRDIV0                (*(volatile unsigned *)0x50000028)
 797
 798#define rULCON1                 (*(volatile unsigned *)0x50004000)
 799#define rUCON1                  (*(volatile unsigned *)0x50004004)
 800#define rUFCON1                 (*(volatile unsigned *)0x50004008)
 801#define rUMCON1                 (*(volatile unsigned *)0x5000400C)
 802#define rUTRSTAT1               (*(volatile unsigned *)0x50004010)
 803#define rUERSTAT1               (*(volatile unsigned *)0x50004014)
 804#define rUFSTAT1                (*(volatile unsigned *)0x50004018)
 805#define rUMSTAT1                (*(volatile unsigned *)0x5000401C)
 806#define rUBRDIV1                (*(volatile unsigned *)0x50004028)
 807
 808#define rULCON2                 (*(volatile unsigned *)0x50008000)
 809#define rUCON2                  (*(volatile unsigned *)0x50008004)
 810#define rUFCON2                 (*(volatile unsigned *)0x50008008)
 811#define rUTRSTAT2               (*(volatile unsigned *)0x50008010)
 812#define rUERSTAT2               (*(volatile unsigned *)0x50008014)
 813#define rUFSTAT2                (*(volatile unsigned *)0x50008018)
 814#define rUBRDIV2                (*(volatile unsigned *)0x50008028)
 815
 816#ifdef __BIG_ENDIAN
 817#define rUTXH0                  (*(volatile unsigned char *)0x50000023)
 818#define rURXH0                  (*(volatile unsigned char *)0x50000027)
 819#define rUTXH1                  (*(volatile unsigned char *)0x50004023)
 820#define rURXH1                  (*(volatile unsigned char *)0x50004027)
 821#define rUTXH2                  (*(volatile unsigned char *)0x50008023)
 822#define rURXH2                  (*(volatile unsigned char *)0x50008027)
 823
 824#define WrUTXH0(ch)             (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
 825#define RdURXH0()               (*(volatile unsigned char *)0x50000027)
 826#define WrUTXH1(ch)             (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
 827#define RdURXH1()               (*(volatile unsigned char *)0x50004027)
 828#define WrUTXH2(ch)             (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
 829#define RdURXH2()               (*(volatile unsigned char *)0x50008027)
 830
 831#define UTXH0                   (0x50000020+3)  /* byte_access address by DMA */
 832#define URXH0                   (0x50000024+3)
 833#define UTXH1                   (0x50004020+3)
 834#define URXH1                   (0x50004024+3)
 835#define UTXH2                   (0x50008020+3)
 836#define URXH2                   (0x50008024+3)
 837
 838#else /* Little Endian */
 839#define rUTXH0                  (*(volatile unsigned char *)0x50000020)
 840#define rURXH0                  (*(volatile unsigned char *)0x50000024)
 841#define rUTXH1                  (*(volatile unsigned char *)0x50004020)
 842#define rURXH1                  (*(volatile unsigned char *)0x50004024)
 843#define rUTXH2                  (*(volatile unsigned char *)0x50008020)
 844#define rURXH2                  (*(volatile unsigned char *)0x50008024)
 845
 846#define WrUTXH0(ch)             (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
 847#define RdURXH0()               (*(volatile unsigned char *)0x50000024)
 848#define WrUTXH1(ch)             (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
 849#define RdURXH1()               (*(volatile unsigned char *)0x50004024)
 850#define WrUTXH2(ch)             (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
 851#define RdURXH2()               (*(volatile unsigned char *)0x50008024)
 852
 853#define UTXH0                   (0x50000020)    /* byte_access address by DMA */
 854#define URXH0                   (0x50000024)
 855#define UTXH1                   (0x50004020)
 856#define URXH1                   (0x50004024)
 857#define UTXH2                   (0x50008020)
 858#define URXH2                   (0x50008024)
 859#endif
 860
 861
 862/* PWM TIMER */
 863#define rTCFG0                  (*(volatile unsigned *)0x51000000)
 864#define rTCFG1                  (*(volatile unsigned *)0x51000004)
 865#define rTCON                   (*(volatile unsigned *)0x51000008)
 866#define rTCNTB0                 (*(volatile unsigned *)0x5100000C)
 867#define rTCMPB0                 (*(volatile unsigned *)0x51000010)
 868#define rTCNTO0                 (*(volatile unsigned *)0x51000014)
 869#define rTCNTB1                 (*(volatile unsigned *)0x51000018)
 870#define rTCMPB1                 (*(volatile unsigned *)0x5100001C)
 871#define rTCNTO1                 (*(volatile unsigned *)0x51000020)
 872#define rTCNTB2                 (*(volatile unsigned *)0x51000024)
 873#define rTCMPB2                 (*(volatile unsigned *)0x51000028)
 874#define rTCNTO2                 (*(volatile unsigned *)0x5100002C)
 875#define rTCNTB3                 (*(volatile unsigned *)0x51000030)
 876#define rTCMPB3                 (*(volatile unsigned *)0x51000034)
 877#define rTCNTO3                 (*(volatile unsigned *)0x51000038)
 878#define rTCNTB4                 (*(volatile unsigned *)0x5100003C)
 879#define rTCNTO4                 (*(volatile unsigned *)0x51000040)
 880
 881
 882/* USB DEVICE */
 883#ifdef __BIG_ENDIAN
 884#define rFUNC_ADDR_REG          (*(volatile unsigned char *)0x52000143)
 885#define rPWR_REG                (*(volatile unsigned char *)0x52000147)
 886#define rEP_INT_REG             (*(volatile unsigned char *)0x5200014B)
 887#define rUSB_INT_REG            (*(volatile unsigned char *)0x5200015B)
 888#define rEP_INT_EN_REG          (*(volatile unsigned char *)0x5200015F)
 889#define rUSB_INT_EN_REG         (*(volatile unsigned char *)0x5200016F)
 890#define rFRAME_NUM1_REG         (*(volatile unsigned char *)0x52000173)
 891#define rFRAME_NUM2_REG         (*(volatile unsigned char *)0x52000177)
 892#define rINDEX_REG              (*(volatile unsigned char *)0x5200017B)
 893#define rMAXP_REG               (*(volatile unsigned char *)0x52000183)
 894#define rEP0_CSR                (*(volatile unsigned char *)0x52000187)
 895#define rIN_CSR1_REG            (*(volatile unsigned char *)0x52000187)
 896#define rIN_CSR2_REG            (*(volatile unsigned char *)0x5200018B)
 897#define rOUT_CSR1_REG           (*(volatile unsigned char *)0x52000193)
 898#define rOUT_CSR2_REG           (*(volatile unsigned char *)0x52000197)
 899#define rOUT_FIFO_CNT1_REG      (*(volatile unsigned char *)0x5200019B)
 900#define rOUT_FIFO_CNT2_REG      (*(volatile unsigned char *)0x5200019F)
 901#define rEP0_FIFO               (*(volatile unsigned char *)0x520001C3)
 902#define rEP1_FIFO               (*(volatile unsigned char *)0x520001C7)
 903#define rEP2_FIFO               (*(volatile unsigned char *)0x520001CB)
 904#define rEP3_FIFO               (*(volatile unsigned char *)0x520001CF)
 905#define rEP4_FIFO               (*(volatile unsigned char *)0x520001D3)
 906#define rEP1_DMA_CON            (*(volatile unsigned char *)0x52000203)
 907#define rEP1_DMA_UNIT           (*(volatile unsigned char *)0x52000207)
 908#define rEP1_DMA_FIFO           (*(volatile unsigned char *)0x5200020B)
 909#define rEP1_DMA_TX_LO          (*(volatile unsigned char *)0x5200020F)
 910#define rEP1_DMA_TX_MD          (*(volatile unsigned char *)0x52000213)
 911#define rEP1_DMA_TX_HI          (*(volatile unsigned char *)0x52000217)
 912#define rEP2_DMA_CON            (*(volatile unsigned char *)0x5200021B)
 913#define rEP2_DMA_UNIT           (*(volatile unsigned char *)0x5200021F)
 914#define rEP2_DMA_FIFO           (*(volatile unsigned char *)0x52000223)
 915#define rEP2_DMA_TX_LO          (*(volatile unsigned char *)0x52000227)
 916#define rEP2_DMA_TX_MD          (*(volatile unsigned char *)0x5200022B)
 917#define rEP2_DMA_TX_HI          (*(volatile unsigned char *)0x5200022F)
 918#define rEP3_DMA_CON            (*(volatile unsigned char *)0x52000243)
 919#define rEP3_DMA_UNIT           (*(volatile unsigned char *)0x52000247)
 920#define rEP3_DMA_FIFO           (*(volatile unsigned char *)0x5200024B)
 921#define rEP3_DMA_TX_LO          (*(volatile unsigned char *)0x5200024F)
 922#define rEP3_DMA_TX_MD          (*(volatile unsigned char *)0x52000253)
 923#define rEP3_DMA_TX_HI          (*(volatile unsigned char *)0x52000257)
 924#define rEP4_DMA_CON            (*(volatile unsigned char *)0x5200025B)
 925#define rEP4_DMA_UNIT           (*(volatile unsigned char *)0x5200025F)
 926#define rEP4_DMA_FIFO           (*(volatile unsigned char *)0x52000263)
 927#define rEP4_DMA_TX_LO          (*(volatile unsigned char *)0x52000267)
 928#define rEP4_DMA_TX_MD          (*(volatile unsigned char *)0x5200026B)
 929#define rEP4_DMA_TX_HI          (*(volatile unsigned char *)0x5200026F)
 930#else /*  little endian */
 931#define rFUNC_ADDR_REG          (*(volatile unsigned char *)0x52000140)
 932#define rPWR_REG                (*(volatile unsigned char *)0x52000144)
 933#define rEP_INT_REG             (*(volatile unsigned char *)0x52000148)
 934#define rUSB_INT_REG            (*(volatile unsigned char *)0x52000158)
 935#define rEP_INT_EN_REG          (*(volatile unsigned char *)0x5200015C)
 936#define rUSB_INT_EN_REG         (*(volatile unsigned char *)0x5200016C)
 937#define rFRAME_NUM1_REG         (*(volatile unsigned char *)0x52000170)
 938#define rFRAME_NUM2_REG         (*(volatile unsigned char *)0x52000174)
 939#define rINDEX_REG              (*(volatile unsigned char *)0x52000178)
 940#define rMAXP_REG               (*(volatile unsigned char *)0x52000180)
 941#define rEP0_CSR                (*(volatile unsigned char *)0x52000184)
 942#define rIN_CSR1_REG            (*(volatile unsigned char *)0x52000184)
 943#define rIN_CSR2_REG            (*(volatile unsigned char *)0x52000188)
 944#define rOUT_CSR1_REG           (*(volatile unsigned char *)0x52000190)
 945#define rOUT_CSR2_REG           (*(volatile unsigned char *)0x52000194)
 946#define rOUT_FIFO_CNT1_REG      (*(volatile unsigned char *)0x52000198)
 947#define rOUT_FIFO_CNT2_REG      (*(volatile unsigned char *)0x5200019C)
 948#define rEP0_FIFO               (*(volatile unsigned char *)0x520001C0)
 949#define rEP1_FIFO               (*(volatile unsigned char *)0x520001C4)
 950#define rEP2_FIFO               (*(volatile unsigned char *)0x520001C8)
 951#define rEP3_FIFO               (*(volatile unsigned char *)0x520001CC)
 952#define rEP4_FIFO               (*(volatile unsigned char *)0x520001D0)
 953#define rEP1_DMA_CON            (*(volatile unsigned char *)0x52000200)
 954#define rEP1_DMA_UNIT           (*(volatile unsigned char *)0x52000204)
 955#define rEP1_DMA_FIFO           (*(volatile unsigned char *)0x52000208)
 956#define rEP1_DMA_TX_LO          (*(volatile unsigned char *)0x5200020C)
 957#define rEP1_DMA_TX_MD          (*(volatile unsigned char *)0x52000210)
 958#define rEP1_DMA_TX_HI          (*(volatile unsigned char *)0x52000214)
 959#define rEP2_DMA_CON            (*(volatile unsigned char *)0x52000218)
 960#define rEP2_DMA_UNIT           (*(volatile unsigned char *)0x5200021C)
 961#define rEP2_DMA_FIFO           (*(volatile unsigned char *)0x52000220)
 962#define rEP2_DMA_TX_LO          (*(volatile unsigned char *)0x52000224)
 963#define rEP2_DMA_TX_MD          (*(volatile unsigned char *)0x52000228)
 964#define rEP2_DMA_TX_HI          (*(volatile unsigned char *)0x5200022C)
 965#define rEP3_DMA_CON            (*(volatile unsigned char *)0x52000240)
 966#define rEP3_DMA_UNIT           (*(volatile unsigned char *)0x52000244)
 967#define rEP3_DMA_FIFO           (*(volatile unsigned char *)0x52000248)
 968#define rEP3_DMA_TX_LO          (*(volatile unsigned char *)0x5200024C)
 969#define rEP3_DMA_TX_MD          (*(volatile unsigned char *)0x52000250)
 970#define rEP3_DMA_TX_HI          (*(volatile unsigned char *)0x52000254)
 971#define rEP4_DMA_CON            (*(volatile unsigned char *)0x52000258)
 972#define rEP4_DMA_UNIT           (*(volatile unsigned char *)0x5200025C)
 973#define rEP4_DMA_FIFO           (*(volatile unsigned char *)0x52000260)
 974#define rEP4_DMA_TX_LO          (*(volatile unsigned char *)0x52000264)
 975#define rEP4_DMA_TX_MD          (*(volatile unsigned char *)0x52000268)
 976#define rEP4_DMA_TX_HI          (*(volatile unsigned char *)0x5200026C)
 977#endif /*  __BIG_ENDIAN */
 978
 979
 980/* WATCH DOG TIMER */
 981#define rWTCON                  (*(volatile unsigned *)0x53000000)
 982#define rWTDAT                  (*(volatile unsigned *)0x53000004)
 983#define rWTCNT                  (*(volatile unsigned *)0x53000008)
 984
 985
 986/* IIC */
 987#define rIICCON                 (*(volatile unsigned *)0x54000000)
 988#define rIICSTAT                (*(volatile unsigned *)0x54000004)
 989#define rIICADD                 (*(volatile unsigned *)0x54000008)
 990#define rIICDS                  (*(volatile unsigned *)0x5400000C)
 991
 992
 993/* IIS */
 994#define rIISCON                 (*(volatile unsigned *)0x55000000)
 995#define rIISMOD                 (*(volatile unsigned *)0x55000004)
 996#define rIISPSR                 (*(volatile unsigned *)0x55000008)
 997#define rIISFCON                (*(volatile unsigned *)0x5500000C)
 998
 999#ifdef __BIG_ENDIAN
1000#define IISFIF                  ((volatile unsigned short *)0x55000012)

1001#else /*  little endian */
1002#define IISFIF                  ((volatile unsigned short *)0x55000010)
1003#endif
1004
1005
1006/* I/O PORT */
1007#define rGPACON                 (*(volatile unsigned *)0x56000000)
1008#define rGPADAT                 (*(volatile unsigned *)0x56000004)
1009
1010#define rGPBCON                 (*(volatile unsigned *)0x56000010)
1011#define rGPBDAT                 (*(volatile unsigned *)0x56000014)
1012#define rGPBUP                  (*(volatile unsigned *)0x56000018)
1013
1014#define rGPCCON                 (*(volatile unsigned *)0x56000020)
1015#define rGPCDAT                 (*(volatile unsigned *)0x56000024)
1016#define rGPCUP                  (*(volatile unsigned *)0x56000028)
1017
1018#define rGPDCON                 (*(volatile unsigned *)0x56000030)
1019#define rGPDDAT                 (*(volatile unsigned *)0x56000034)
1020#define rGPDUP                  (*(volatile unsigned *)0x56000038)
1021
1022#define rGPECON                 (*(volatile unsigned *)0x56000040)
1023#define rGPEDAT                 (*(volatile unsigned *)0x56000044)
1024#define rGPEUP                  (*(volatile unsigned *)0x56000048)
1025
1026#define rGPFCON                 (*(volatile unsigned *)0x56000050)
1027#define rGPFDAT                 (*(volatile unsigned *)0x56000054)
1028#define rGPFUP                  (*(volatile unsigned *)0x56000058)
1029
1030#define rGPGCON                 (*(volatile unsigned *)0x56000060)
1031#define rGPGDAT                 (*(volatile unsigned *)0x56000064)
1032#define rGPGUP                  (*(volatile unsigned *)0x56000068)
1033
1034#define rGPHCON                 (*(volatile unsigned *)0x56000070)
1035#define rGPHDAT                 (*(volatile unsigned *)0x56000074)
1036#define rGPHUP                  (*(volatile unsigned *)0x56000078)
1037
1038#define rMISCCR                 (*(volatile unsigned *)0x56000080)
1039#define rDCLKCON                (*(volatile unsigned *)0x56000084)
1040#define rEXTINT0                (*(volatile unsigned *)0x56000088)
1041#define rEXTINT1                (*(volatile unsigned *)0x5600008C)
1042#define rEXTINT2                (*(volatile unsigned *)0x56000090)
1043#define rEINTFLT0               (*(volatile unsigned *)0x56000094)
1044#define rEINTFLT1               (*(volatile unsigned *)0x56000098)
1045#define rEINTFLT2               (*(volatile unsigned *)0x5600009C)
1046#define rEINTFLT3               (*(volatile unsigned *)0x560000A0)
1047#define rEINTMASK               (*(volatile unsigned *)0x560000A4)
1048#define rEINTPEND               (*(volatile unsigned *)0x560000A8)
1049#define rGSTATUS0               (*(volatile unsigned *)0x560000AC)
1050#define rGSTATUS1               (*(volatile unsigned *)0x560000B0)
1051
1052
1053/* RTC */
1054#ifdef __BIG_ENDIAN
1055#define rRTCCON                 (*(volatile unsigned char *)0x57000043)
1056#define rTICNT                  (*(volatile unsigned char *)0x57000047)
1057#define rRTCALM                 (*(volatile unsigned char *)0x57000053)
1058#define rALMSEC                 (*(volatile unsigned char *)0x57000057)
1059#define rALMMIN                 (*(volatile unsigned char *)0x5700005B)
1060#define rALMHOUR                (*(volatile unsigned char *)0x5700005F)
1061#define rALMDATE                (*(volatile unsigned char *)0x57000063)
1062#define rALMMON                 (*(volatile unsigned char *)0x57000067)
1063#define rALMYEAR                (*(volatile unsigned char *)0x5700006B)
1064#define rRTCRST                 (*(volatile unsigned char *)0x5700006F)
1065#define rBCDSEC                 (*(volatile unsigned char *)0x57000073)
1066#define rBCDMIN                 (*(volatile unsigned char *)0x57000077)
1067#define rBCDHOUR                (*(volatile unsigned char *)0x5700007B)
1068#define rBCDDATE                (*(volatile unsigned char *)0x5700007F)
1069#define rBCDDAY                 (*(volatile unsigned char *)0x57000083)
1070#define rBCDMON                 (*(volatile unsigned char *)0x57000087)
1071#define rBCDYEAR                (*(volatile unsigned char *)0x5700008B)
1072#else /*  little endian */
1073#define rRTCCON                 (*(volatile unsigned char *)0x57000040)
1074#define rTICNT                  (*(volatile unsigned char *)0x57000044)
1075#define rRTCALM                 (*(volatile unsigned char *)0x57000050)
1076#define rALMSEC                 (*(volatile unsigned char *)0x57000054)
1077#define rALMMIN                 (*(volatile unsigned char *)0x57000058)
1078#define rALMHOUR                (*(volatile unsigned char *)0x5700005C)
1079#define rALMDATE                (*(volatile unsigned char *)0x57000060)
1080#define rALMMON                 (*(volatile unsigned char *)0x57000064)
1081#define rALMYEAR                (*(volatile unsigned char *)0x57000068)
1082#define rRTCRST                 (*(volatile unsigned char *)0x5700006C)
1083#define rBCDSEC                 (*(volatile unsigned char *)0x57000070)
1084#define rBCDMIN                 (*(volatile unsigned char *)0x57000074)
1085#define rBCDHOUR                (*(volatile unsigned char *)0x57000078)
1086#define rBCDDATE                (*(volatile unsigned char *)0x5700007C)
1087#define rBCDDAY                 (*(volatile unsigned char *)0x57000080)
1088#define rBCDMON                 (*(volatile unsigned char *)0x57000084)
1089#define rBCDYEAR                (*(volatile unsigned char *)0x57000088)
1090#endif
1091
1092
1093/* ADC */
1094#define rADCCON                 (*(volatile unsigned *)0x58000000)
1095#define rADCTSC                 (*(volatile unsigned *)0x58000004)
1096#define rADCDLY                 (*(volatile unsigned *)0x58000008)
1097#define rADCDAT0                (*(volatile unsigned *)0x5800000C)
1098#define rADCDAT1                (*(volatile unsigned *)0x58000010)
1099
1100
1101/* SPI */
1102#define rSPCON0                 (*(volatile unsigned *)0x59000000)
1103#define rSPSTA0                 (*(volatile unsigned *)0x59000004)
1104#define rSPPIN0                 (*(volatile unsigned *)0x59000008)
1105#define rSPPRE0                 (*(volatile unsigned *)0x5900000C)
1106#define rSPTDAT0                (*(volatile unsigned *)0x59000010)
1107#define rSPRDAT0                (*(volatile unsigned *)0x59000014)
1108#define rSPCON1                 (*(volatile unsigned *)0x59000020)
1109#define rSPSTA1                 (*(volatile unsigned *)0x59000024)
1110#define rSPPIN1                 (*(volatile unsigned *)0x59000028)
1111#define rSPPRE1                 (*(volatile unsigned *)0x5900002C)
1112#define rSPTDAT1                (*(volatile unsigned *)0x59000030)
1113#define rSPRDAT1                (*(volatile unsigned *)0x59000034)
1114
1115
1116/* SD INTERFACE */
1117#define rSDICON                 (*(volatile unsigned *)0x5A000000)
1118#define rSDIPRE                 (*(volatile unsigned *)0x5A000004)
1119#define rSDICmdArg              (*(volatile unsigned *)0x5A000008)
1120#define rSDICmdCon              (*(volatile unsigned *)0x5A00000C)
1121#define rSDICmdSta              (*(volatile unsigned *)0x5A000010)
1122#define rSDIRSP0                (*(volatile unsigned *)0x5A000014)
1123#define rSDIRSP1                (*(volatile unsigned *)0x5A000018)
1124#define rSDIRSP2                (*(volatile unsigned *)0x5A00001C)
1125#define rSDIRSP3                (*(volatile unsigned *)0x5A000020)
1126#define rSDIDTimer              (*(volatile unsigned *)0x5A000024)
1127#define rSDIBSize               (*(volatile unsigned *)0x5A000028)
1128#define rSDIDatCon              (*(volatile unsigned *)0x5A00002C)
1129#define rSDIDatCnt              (*(volatile unsigned *)0x5A000030)
1130#define rSDIDatSta              (*(volatile unsigned *)0x5A000034)
1131#define rSDIFSTA                (*(volatile unsigned *)0x5A000038)
1132#ifdef __BIG_ENDIAN
1133#define rSDIDAT                 (*(volatile unsigned char *)0x5A00003F)
1134#else
1135#define rSDIDAT                 (*(volatile unsigned char *)0x5A00003C)
1136#endif
1137#define rSDIIntMsk              (*(volatile unsigned *)0x5A000040)
1138
1139#endif
1140
1141#endif /*__S3C24X0_H__*/
1142