LXR uboot/board/atmel/at91cap9adk/at91cap9adk.c

   1/*
   2 * (C) Copyright 2007-2008
   3 * Stelian Pop <stelian.pop@leadtechdesign.com>
   4 * Lead Tech Design <www.leadtechdesign.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <common.h>
  26#include <asm/arch/at91cap9.h>
  27#include <asm/arch/at91cap9_matrix.h>
  28#include <asm/arch/at91sam9_smc.h>
  29#include <asm/arch/at91_common.h>
  30#include <asm/arch/at91_pmc.h>
  31#include <asm/arch/at91_rstc.h>
  32#include <asm/arch/clk.h>
  33#include <asm/arch/gpio.h>
  34#include <asm/arch/io.h>
  35#include <asm/arch/hardware.h>
  36#include <lcd.h>
  37#include <atmel_lcdc.h>
  38#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  39#include <net.h>
  40#endif
  41#include <netdev.h>
  42
  43#define MP_BLOCK_3_BASE 0xFDF00000
  44
  45DECLARE_GLOBAL_DATA_PTR;
  46
  47/* ------------------------------------------------------------------------- */
  48/*
  49 * Miscelaneous platform dependent initialisations
  50 */
  51
  52static void at91cap9_slowclock_hw_init(void)
  53{
  54        /*
  55         * On AT91CAP9 revC CPUs, the slow clock can be based on an
  56         * internal impreciseRC oscillator or an external 32kHz oscillator.
  57         * Switch to the latter.
  58         */
  59#define ARCH_ID_AT91CAP9_REVB   0x399
  60#define ARCH_ID_AT91CAP9_REVC   0x601
  61        if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
  62                unsigned i, tmp = at91_sys_read(AT91_SCKCR);
  63                if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
  64                        timer_init();
  65                        tmp |= AT91CAP9_SCKCR_OSC32EN;
  66                        at91_sys_write(AT91_SCKCR, tmp);
  67                        for (i = 0; i < 1200; i++)
  68                                udelay(1000);
  69                        tmp |= AT91CAP9_SCKCR_OSCSEL_32;
  70                        at91_sys_write(AT91_SCKCR, tmp);
  71                        udelay(200);
  72                        tmp &= ~AT91CAP9_SCKCR_RCEN;
  73                        at91_sys_write(AT91_SCKCR, tmp);
  74                }
  75        }
  76}
  77
  78static void at91cap9_nor_hw_init(void)
  79{
  80        unsigned long csa;
  81
  82        /* Ensure EBI supply is 3.3V */
  83        csa = at91_sys_read(AT91_MATRIX_EBICSA);
  84        at91_sys_write(AT91_MATRIX_EBICSA,
  85                       csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
  86        /* Configure SMC CS0 for parallel flash */
  87        at91_sys_write(AT91_SMC_SETUP(0),
  88                       AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
  89                       AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
  90        at91_sys_write(AT91_SMC_PULSE(0),
  91                       AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
  92                       AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
  93        at91_sys_write(AT91_SMC_CYCLE(0),
  94                       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
  95        at91_sys_write(AT91_SMC_MODE(0),
  96                       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  97                       AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
  98                       AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
  99}
 100
 101#ifdef CONFIG_CMD_NAND
 102static void at91cap9_nand_hw_init(void)
 103{
 104        unsigned long csa;
 105
 106        /* Enable CS3 */
 107        csa = at91_sys_read(AT91_MATRIX_EBICSA);
 108        at91_sys_write(AT91_MATRIX_EBICSA,
 109                       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
 110                       AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 111
 112        /* Configure SMC CS3 for NAND/SmartMedia */
 113        at91_sys_write(AT91_SMC_SETUP(3),
 114                       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
 115                       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
 116        at91_sys_write(AT91_SMC_PULSE(3),
 117                       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
 118                       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
 119        at91_sys_write(AT91_SMC_CYCLE(3),
 120                       AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
 121        at91_sys_write(AT91_SMC_MODE(3),
 122                       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 123                       AT91_SMC_EXNWMODE_DISABLE |
 124#ifdef CONFIG_SYS_NAND_DBW_16
 125                       AT91_SMC_DBW_16 |
 126#else /* CONFIG_SYS_NAND_DBW_8 */
 127                       AT91_SMC_DBW_8 |
 128#endif
 129                       AT91_SMC_TDF_(1));
 130
 131        at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
 132
 133        /* RDY/BSY is not connected */
 134
 135        /* Enable NandFlash */
 136        at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 137}
 138#endif
 139
 140#ifdef CONFIG_MACB
 141static void at91cap9_macb_hw_init(void)
 142{
 143        /* Enable clock */
 144        at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
 145
 146        /*
 147         * Disable pull-up on:
 148         *      RXDV (PB22) => PHY normal mode (not Test mode)
 149         *      ERX0 (PB25) => PHY ADDR0
 150         *      ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
 151         *
 152         * PHY has internal pull-down
 153         */
 154        writel(pin_to_mask(AT91_PIN_PB22) |
 155               pin_to_mask(AT91_PIN_PB25) |
 156               pin_to_mask(AT91_PIN_PB26),
 157               pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 158
 159        /* Need to reset PHY -> 500ms reset */
 160        at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 161                                     (AT91_RSTC_ERSTL & (0x0D << 8)) |
 162                                     AT91_RSTC_URSTEN);
 163
 164        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 165
 166        /* Wait for end hardware reset */
 167        while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 168
 169        /* Restore NRST value */
 170        at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 171                                     (AT91_RSTC_ERSTL & (0x0 << 8)) |
 172                                     AT91_RSTC_URSTEN);
 173
 174        /* Re-enable pull-up */
 175        writel(pin_to_mask(AT91_PIN_PB22) |
 176               pin_to_mask(AT91_PIN_PB25) |
 177               pin_to_mask(AT91_PIN_PB26),
 178               pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
 179
 180        at91_macb_hw_init();
 181
 182        /* Unlock EMAC, 3 0 2 1 sequence */
 183#define MP_MAC_KEY0     0x5969cb2a
 184#define MP_MAC_KEY1     0xb4a1872e
 185#define MP_MAC_KEY2     0x05683fbc
 186#define MP_MAC_KEY3     0x3634fba4
 187#define UNLOCK_MAC      0x00000008
 188        writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
 189        writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
 190        writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
 191        writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
 192        writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
 193}
 194#endif
 195
 196#ifdef CONFIG_USB_OHCI_NEW
 197static void at91cap9_uhp_hw_init(void)
 198{
 199        /* Unlock USB OHCI, 3 2 0 1 sequence */
 200#define MP_OHCI_KEY0    0x896c11ca
 201#define MP_OHCI_KEY1    0x68ebca21
 202#define MP_OHCI_KEY2    0x4823efbc
 203#define MP_OHCI_KEY3    0x8651aae4
 204#define UNLOCK_OHCI     0x00000010
 205        writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
 206        writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
 207        writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
 208        writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
 209        writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
 210}
 211#endif
 212
 213#ifdef CONFIG_LCD
 214vidinfo_t panel_info = {
 215        vl_col:         240,
 216        vl_row:         320,
 217        vl_clk:         4965000,
 218        vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 219                        ATMEL_LCDC_INVFRAME_INVERTED,
 220        vl_bpix:        3,
 221        vl_tft:         1,
 222        vl_hsync_len:   5,
 223        vl_left_margin: 1,
 224        vl_right_margin:33,
 225        vl_vsync_len:   1,
 226        vl_upper_margin:1,
 227        vl_lower_margin:0,
 228        mmio:           AT91CAP9_LCDC_BASE,
 229};
 230
 231void lcd_enable(void)
 232{
 233        at91_set_gpio_value(AT91_PIN_PC0, 0);  /* power up */
 234}
 235
 236void lcd_disable(void)
 237{
 238        at91_set_gpio_value(AT91_PIN_PC0, 1);  /* power down */
 239}
 240
 241static void at91cap9_lcd_hw_init(void)
 242{
 243        at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
 244        at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
 245        at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
 246        at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
 247        at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
 248        at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
 249        at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
 250        at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
 251        at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
 252        at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
 253        at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
 254        at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 255        at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 256        at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 257        at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 258        at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 259        at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
 260        at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
 261        at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
 262        at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
 263        at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
 264        at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
 265
 266        at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
 267
 268        gd->fb_base = 0;
 269}
 270
 271#ifdef CONFIG_LCD_INFO
 272#include <nand.h>
 273#include <version.h>
 274
 275void lcd_show_board_info(void)
 276{
 277        ulong dram_size, nand_size;
 278        int i;
 279        char temp[32];
 280
 281        lcd_printf ("%s\n", U_BOOT_VERSION);
 282        lcd_printf ("(C) 2008 ATMEL Corp\n");
 283        lcd_printf ("at91support@atmel.com\n");
 284        lcd_printf ("%s CPU at %s MHz\n",
 285                AT91_CPU_NAME,
 286                strmhz(temp, get_cpu_clk_rate()));
 287
 288        dram_size = 0;
 289        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 290                dram_size += gd->bd->bi_dram[i].size;
 291        nand_size = 0;
 292        for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 293                nand_size += nand_info[i].size;
 294        lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 295                dram_size >> 20,
 296                nand_size >> 20 );
 297}
 298#endif /* CONFIG_LCD_INFO */
 299#endif
 300
 301int board_init(void)
 302{
 303        /* Enable Ctrlc */
 304        console_init_f();
 305
 306        /* arch number of AT91CAP9ADK-Board */
 307        gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
 308        /* adress of boot parameters */
 309        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 310
 311        at91_serial_hw_init();
 312        at91cap9_slowclock_hw_init();
 313        at91cap9_nor_hw_init();
 314#ifdef CONFIG_CMD_NAND
 315        at91cap9_nand_hw_init();
 316#endif
 317#ifdef CONFIG_HAS_DATAFLASH
 318        at91_spi0_hw_init(1 << 0);
 319#endif
 320#ifdef CONFIG_MACB
 321        at91cap9_macb_hw_init();
 322#endif
 323#ifdef CONFIG_USB_OHCI_NEW
 324        at91cap9_uhp_hw_init();
 325#endif
 326#ifdef CONFIG_LCD
 327        at91cap9_lcd_hw_init();
 328#endif
 329        return 0;
 330}
 331
 332int dram_init(void)
 333{
 334        gd->bd->bi_dram[0].start = PHYS_SDRAM;
 335        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 336        return 0;
 337}
 338
 339#ifdef CONFIG_RESET_PHY_R
 340void reset_phy(void)
 341{
 342#ifdef CONFIG_MACB
 343        /*
 344         * Initialize ethernet HW addr prior to starting Linux,
 345         * needed for nfsroot
 346         */
 347        eth_init(gd->bd);
 348#endif
 349}
 350#endif
 351
 352int board_eth_init(bd_t *bis)
 353{
 354        int rc = 0;
 355#ifdef CONFIG_MACB
 356        rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00);
 357#endif
 358        return rc;
 359}
 360