LXR uboot/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

   1/*
   2 * (C) Copyright 2007-2008
   3 * Stelian Pop <stelian.pop@leadtechdesign.com>
   4 * Lead Tech Design <www.leadtechdesign.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <common.h>
  26#include <asm/sizes.h>
  27#include <asm/arch/at91sam9g45.h>
  28#include <asm/arch/at91sam9_matrix.h>
  29#include <asm/arch/at91sam9_smc.h>
  30#include <asm/arch/at91_common.h>
  31#include <asm/arch/at91_pmc.h>
  32#include <asm/arch/at91_rstc.h>
  33#include <asm/arch/clk.h>
  34#include <asm/arch/gpio.h>
  35#include <asm/arch/io.h>
  36#include <asm/arch/hardware.h>
  37#include <lcd.h>
  38#include <atmel_lcdc.h>
  39#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  40#include <net.h>
  41#endif
  42#include <netdev.h>
  43
  44DECLARE_GLOBAL_DATA_PTR;
  45
  46/* ------------------------------------------------------------------------- */
  47/*
  48 * Miscelaneous platform dependent initialisations
  49 */
  50
  51#ifdef CONFIG_CMD_NAND
  52static void at91sam9m10g45ek_nand_hw_init(void)
  53{
  54        unsigned long csa;
  55
  56        /* Enable CS3 */
  57        csa = at91_sys_read(AT91_MATRIX_EBICSA);
  58        at91_sys_write(AT91_MATRIX_EBICSA,
  59                       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
  60
  61        /* Configure SMC CS3 for NAND/SmartMedia */
  62        at91_sys_write(AT91_SMC_SETUP(3),
  63                       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  64                       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  65        at91_sys_write(AT91_SMC_PULSE(3),
  66                       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
  67                       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
  68        at91_sys_write(AT91_SMC_CYCLE(3),
  69                       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
  70        at91_sys_write(AT91_SMC_MODE(3),
  71                       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  72                       AT91_SMC_EXNWMODE_DISABLE |
  73#ifdef CONFIG_SYS_NAND_DBW_16
  74                       AT91_SMC_DBW_16 |
  75#else /* CONFIG_SYS_NAND_DBW_8 */
  76                       AT91_SMC_DBW_8 |
  77#endif
  78                       AT91_SMC_TDF_(3));
  79
  80        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
  81
  82        /* Configure RDY/BSY */
  83        at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  84
  85        /* Enable NandFlash */
  86        at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  87}
  88#endif
  89
  90#ifdef CONFIG_MACB
  91static void at91sam9m10g45ek_macb_hw_init(void)
  92{
  93        unsigned long rstc;
  94
  95        /* Enable clock */
  96        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
  97
  98        /*
  99         * Disable pull-up on:
 100         *      RXDV (PA15) => PHY normal mode (not Test mode)
 101         *      ERX0 (PA12) => PHY ADDR0
 102         *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
 103         *
 104         * PHY has internal pull-down
 105         */
 106        writel(pin_to_mask(AT91_PIN_PA15) |
 107               pin_to_mask(AT91_PIN_PA12) |
 108               pin_to_mask(AT91_PIN_PA13),
 109               pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 110
 111        rstc = at91_sys_read(AT91_RSTC_MR);
 112
 113        /* Need to reset PHY -> 500ms reset */
 114        at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 115                                     (AT91_RSTC_ERSTL & (0x0D << 8)) |
 116                                     AT91_RSTC_URSTEN);
 117
 118        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 119
 120        /* Wait for end hardware reset */
 121        while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 122
 123        /* Restore NRST value */
 124        at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 125                                     (rstc) |
 126                                     AT91_RSTC_URSTEN);
 127
 128        /* Re-enable pull-up */
 129        writel(pin_to_mask(AT91_PIN_PA15) |
 130               pin_to_mask(AT91_PIN_PA12) |
 131               pin_to_mask(AT91_PIN_PA13),
 132               pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
 133
 134        at91_macb_hw_init();
 135}
 136#endif
 137
 138#ifdef CONFIG_LCD
 139
 140vidinfo_t panel_info = {
 141        vl_col:         480,
 142        vl_row:         272,
 143        vl_clk:         9000000,
 144        vl_sync:        ATMEL_LCDC_INVLINE_NORMAL |
 145                        ATMEL_LCDC_INVFRAME_NORMAL,
 146        vl_bpix:        3,
 147        vl_tft:         1,
 148        vl_hsync_len:   45,
 149        vl_left_margin: 1,
 150        vl_right_margin:1,
 151        vl_vsync_len:   1,
 152        vl_upper_margin:40,
 153        vl_lower_margin:1,
 154        mmio:           AT91SAM9G45_LCDC_BASE,
 155};
 156
 157
 158void lcd_enable(void)
 159{
 160        at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
 161}
 162
 163void lcd_disable(void)
 164{
 165        at91_set_A_periph(AT91_PIN_PE6, 0);     /* power down */
 166}
 167
 168static void at91sam9m10g45ek_lcd_hw_init(void)
 169{
 170        at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 171        at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 172        at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 173        at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 174        at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 175
 176        at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 177        at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 178        at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 179        at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 180        at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 181        at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 182        at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 183        at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 184        at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 185        at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 186        at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 187        at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 188        at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 189        at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 190        at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 191        at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 192        at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 193        at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 194        at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 195        at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 196        at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 197        at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 198        at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 199        at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 200
 201        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
 202
 203        gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 204}
 205
 206#ifdef CONFIG_LCD_INFO
 207#include <nand.h>
 208#include <version.h>
 209
 210void lcd_show_board_info(void)
 211{
 212        ulong dram_size, nand_size;
 213        int i;
 214        char temp[32];
 215
 216        lcd_printf ("%s\n", U_BOOT_VERSION);
 217        lcd_printf ("(C) 2008 ATMEL Corp\n");
 218        lcd_printf ("at91support@atmel.com\n");
 219        lcd_printf ("%s CPU at %s MHz\n",
 220                AT91_CPU_NAME,
 221                strmhz(temp, get_cpu_clk_rate()));
 222
 223        dram_size = 0;
 224        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 225                dram_size += gd->bd->bi_dram[i].size;
 226        nand_size = 0;
 227        for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 228                nand_size += nand_info[i].size;
 229        lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 230                dram_size >> 20,
 231                nand_size >> 20 );
 232}
 233#endif /* CONFIG_LCD_INFO */
 234#endif
 235
 236int board_init(void)
 237{
 238        /* Enable Ctrlc */
 239        console_init_f();
 240
 241        /* arch number of AT91SAM9M10G45EK-Board */
 242#ifdef CONFIG_AT91SAM9M10G45EK
 243        gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
 244#elif defined CONFIG_AT91SAM9G45EKES
 245        gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
 246#endif
 247        /* adress of boot parameters */
 248        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 249
 250        at91_serial_hw_init();
 251#ifdef CONFIG_CMD_NAND
 252        at91sam9m10g45ek_nand_hw_init();
 253#endif
 254#ifdef CONFIG_HAS_DATAFLASH
 255        at91_spi0_hw_init(1 << 0);
 256#endif
 257#ifdef CONFIG_ATMEL_SPI
 258        at91_spi0_hw_init(1 << 4);
 259#endif
 260
 261#ifdef CONFIG_MACB
 262        at91sam9m10g45ek_macb_hw_init();
 263#endif
 264
 265#ifdef CONFIG_LCD
 266        at91sam9m10g45ek_lcd_hw_init();
 267#endif
 268        return 0;
 269}
 270
 271int dram_init(void)
 272{
 273        gd->bd->bi_dram[0].start = PHYS_SDRAM;
 274        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 275        return 0;
 276}
 277
 278#ifdef CONFIG_RESET_PHY_R
 279void reset_phy(void)
 280{
 281#ifdef CONFIG_MACB
 282        /*
 283         * Initialize ethernet HW addr prior to starting Linux,
 284         * needed for nfsroot
 285         */
 286        eth_init(gd->bd);
 287#endif
 288}
 289#endif
 290
 291int board_eth_init(bd_t *bis)
 292{
 293        int rc = 0;
 294#ifdef CONFIG_MACB
 295        rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
 296#endif
 297        return rc;
 298}
 299
 300/* SPI chip select control */
 301#ifdef CONFIG_ATMEL_SPI
 302#include <spi.h>
 303
 304int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 305{
 306        return bus == 0 && cs < 2;
 307}
 308
 309void spi_cs_activate(struct spi_slave *slave)
 310{
 311        switch(slave->cs) {
 312                case 1:
 313                        at91_set_gpio_output(AT91_PIN_PB18, 0);
 314                        break;
 315                case 0:
 316                default:
 317                        at91_set_gpio_output(AT91_PIN_PB3, 0);
 318                        break;
 319        }
 320}
 321
 322void spi_cs_deactivate(struct spi_slave *slave)
 323{
 324        switch(slave->cs) {
 325                case 1:
 326                        at91_set_gpio_output(AT91_PIN_PB18, 1);
 327                        break;
 328                case 0:
 329                default:
 330                        at91_set_gpio_output(AT91_PIN_PB3, 1);
 331                break;
 332        }
 333}
 334#endif /* CONFIG_ATMEL_SPI */
 335