LXR uboot/board/freescale/mpc8360erdk/mpc8360erdk.c

   1/*
   2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3 *                    Dave Liu <daveliu@freescale.com>
   4 *
   5 * Copyright (C) 2007 Logic Product Development, Inc.
   6 *                    Peter Barada <peterb@logicpd.com>
   7 *
   8 * Copyright (C) 2007 MontaVista Software, Inc.
   9 *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 */
  16
  17#include <common.h>
  18#include <ioports.h>
  19#include <mpc83xx.h>
  20#include <i2c.h>
  21#include <miiphy.h>
  22#include <asm/io.h>
  23#include <asm/mmu.h>
  24#include <pci.h>
  25#include <libfdt.h>
  26
  27const qe_iop_conf_t qe_iop_conf_tab[] = {
  28        /* MDIO */
  29        {0,  1, 3, 0, 2}, /* MDIO */
  30        {0,  2, 1, 0, 1}, /* MDC */
  31
  32        /* UCC1 - UEC (Gigabit) */
  33        {0,  3, 1, 0, 1}, /* TxD0 */
  34        {0,  4, 1, 0, 1}, /* TxD1 */
  35        {0,  5, 1, 0, 1}, /* TxD2 */
  36        {0,  6, 1, 0, 1}, /* TxD3 */
  37        {0,  9, 2, 0, 1}, /* RxD0 */
  38        {0, 10, 2, 0, 1}, /* RxD1 */
  39        {0, 11, 2, 0, 1}, /* RxD2 */
  40        {0, 12, 2, 0, 1}, /* RxD3 */
  41        {0,  7, 1, 0, 1}, /* TX_EN */
  42        {0,  8, 1, 0, 1}, /* TX_ER */
  43        {0, 15, 2, 0, 1}, /* RX_DV */
  44        {0,  0, 2, 0, 1}, /* RX_CLK */
  45        {2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
  46        {2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
  47
  48        /* UCC2 - UEC (Gigabit) */
  49        {0, 17, 1, 0, 1}, /* TxD0 */
  50        {0, 18, 1, 0, 1}, /* TxD1 */
  51        {0, 19, 1, 0, 1}, /* TxD2 */
  52        {0, 20, 1, 0, 1}, /* TxD3 */
  53        {0, 23, 2, 0, 1}, /* RxD0 */
  54        {0, 24, 2, 0, 1}, /* RxD1 */
  55        {0, 25, 2, 0, 1}, /* RxD2 */
  56        {0, 26, 2, 0, 1}, /* RxD3 */
  57        {0, 21, 1, 0, 1}, /* TX_EN */
  58        {0, 22, 1, 0, 1}, /* TX_ER */
  59        {0, 29, 2, 0, 1}, /* RX_DV */
  60        {0, 31, 2, 0, 1}, /* RX_CLK */
  61        {2,  2, 1, 0, 2}, /* GTX_CLK - CLK10 */
  62        {2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
  63
  64        /* UCC7 - UEC */
  65        {4,  0, 1, 0, 1}, /* TxD0 */
  66        {4,  1, 1, 0, 1}, /* TxD1 */
  67        {4,  2, 1, 0, 1}, /* TxD2 */
  68        {4,  3, 1, 0, 1}, /* TxD3 */
  69        {4,  6, 2, 0, 1}, /* RxD0 */
  70        {4,  7, 2, 0, 1}, /* RxD1 */
  71        {4,  8, 2, 0, 1}, /* RxD2 */
  72        {4,  9, 2, 0, 1}, /* RxD3 */
  73        {4,  4, 1, 0, 1}, /* TX_EN */
  74        {4,  5, 1, 0, 1}, /* TX_ER */
  75        {4, 12, 2, 0, 1}, /* RX_DV */
  76        {4, 13, 2, 0, 1}, /* RX_ER */
  77        {4, 10, 2, 0, 1}, /* COL */
  78        {4, 11, 2, 0, 1}, /* CRS */
  79        {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
  80        {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
  81
  82        /* UCC4 - UEC */
  83        {1, 14, 1, 0, 1}, /* TxD0 */
  84        {1, 15, 1, 0, 1}, /* TxD1 */
  85        {1, 16, 1, 0, 1}, /* TxD2 */
  86        {1, 17, 1, 0, 1}, /* TxD3 */
  87        {1, 20, 2, 0, 1}, /* RxD0 */
  88        {1, 21, 2, 0, 1}, /* RxD1 */
  89        {1, 22, 2, 0, 1}, /* RxD2 */
  90        {1, 23, 2, 0, 1}, /* RxD3 */
  91        {1, 18, 1, 0, 1}, /* TX_EN */
  92        {1, 19, 1, 0, 2}, /* TX_ER */
  93        {1, 26, 2, 0, 1}, /* RX_DV */
  94        {1, 27, 2, 0, 1}, /* RX_ER */
  95        {1, 24, 2, 0, 1}, /* COL */
  96        {1, 25, 2, 0, 1}, /* CRS */
  97        {2,  6, 2, 0, 1}, /* TX_CLK - CLK7 */
  98        {2,  7, 2, 0, 1}, /* RX_CLK - CLK8 */
  99
 100        /* PCI1 */
 101        {5,  4, 2, 0, 3}, /* PCI_M66EN */
 102        {5,  5, 1, 0, 3}, /* PCI_INTA */
 103        {5,  6, 1, 0, 3}, /* PCI_RSTO */
 104        {5,  7, 3, 0, 3}, /* PCI_C_BE0 */
 105        {5,  8, 3, 0, 3}, /* PCI_C_BE1 */
 106        {5,  9, 3, 0, 3}, /* PCI_C_BE2 */
 107        {5, 10, 3, 0, 3}, /* PCI_C_BE3 */
 108        {5, 11, 3, 0, 3}, /* PCI_PAR */
 109        {5, 12, 3, 0, 3}, /* PCI_FRAME */
 110        {5, 13, 3, 0, 3}, /* PCI_TRDY */
 111        {5, 14, 3, 0, 3}, /* PCI_IRDY */
 112        {5, 15, 3, 0, 3}, /* PCI_STOP */
 113        {5, 16, 3, 0, 3}, /* PCI_DEVSEL */
 114        {5, 17, 0, 0, 0}, /* PCI_IDSEL */
 115        {5, 18, 3, 0, 3}, /* PCI_SERR */
 116        {5, 19, 3, 0, 3}, /* PCI_PERR */
 117        {5, 20, 3, 0, 3}, /* PCI_REQ0 */
 118        {5, 21, 2, 0, 3}, /* PCI_REQ1 */
 119        {5, 22, 2, 0, 3}, /* PCI_GNT2 */
 120        {5, 23, 3, 0, 3}, /* PCI_GNT0 */
 121        {5, 24, 1, 0, 3}, /* PCI_GNT1 */
 122        {5, 25, 1, 0, 3}, /* PCI_GNT2 */
 123        {5, 26, 0, 0, 0}, /* PCI_CLK0 */
 124        {5, 27, 0, 0, 0}, /* PCI_CLK1 */
 125        {5, 28, 0, 0, 0}, /* PCI_CLK2 */
 126        {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
 127        {6,  0, 3, 0, 3}, /* PCI_AD0 */
 128        {6,  1, 3, 0, 3}, /* PCI_AD1 */
 129        {6,  2, 3, 0, 3}, /* PCI_AD2 */
 130        {6,  3, 3, 0, 3}, /* PCI_AD3 */
 131        {6,  4, 3, 0, 3}, /* PCI_AD4 */
 132        {6,  5, 3, 0, 3}, /* PCI_AD5 */
 133        {6,  6, 3, 0, 3}, /* PCI_AD6 */
 134        {6,  7, 3, 0, 3}, /* PCI_AD7 */
 135        {6,  8, 3, 0, 3}, /* PCI_AD8 */
 136        {6,  9, 3, 0, 3}, /* PCI_AD9 */
 137        {6, 10, 3, 0, 3}, /* PCI_AD10 */
 138        {6, 11, 3, 0, 3}, /* PCI_AD11 */
 139        {6, 12, 3, 0, 3}, /* PCI_AD12 */
 140        {6, 13, 3, 0, 3}, /* PCI_AD13 */
 141        {6, 14, 3, 0, 3}, /* PCI_AD14 */
 142        {6, 15, 3, 0, 3}, /* PCI_AD15 */
 143        {6, 16, 3, 0, 3}, /* PCI_AD16 */
 144        {6, 17, 3, 0, 3}, /* PCI_AD17 */
 145        {6, 18, 3, 0, 3}, /* PCI_AD18 */
 146        {6, 19, 3, 0, 3}, /* PCI_AD19 */
 147        {6, 20, 3, 0, 3}, /* PCI_AD20 */
 148        {6, 21, 3, 0, 3}, /* PCI_AD21 */
 149        {6, 22, 3, 0, 3}, /* PCI_AD22 */
 150        {6, 23, 3, 0, 3}, /* PCI_AD23 */
 151        {6, 24, 3, 0, 3}, /* PCI_AD24 */
 152        {6, 25, 3, 0, 3}, /* PCI_AD25 */
 153        {6, 26, 3, 0, 3}, /* PCI_AD26 */
 154        {6, 27, 3, 0, 3}, /* PCI_AD27 */
 155        {6, 28, 3, 0, 3}, /* PCI_AD28 */
 156        {6, 29, 3, 0, 3}, /* PCI_AD29 */
 157        {6, 30, 3, 0, 3}, /* PCI_AD30 */
 158        {6, 31, 3, 0, 3}, /* PCI_AD31 */
 159
 160        /* NAND */
 161        {4, 18, 2, 0, 0}, /* NAND_RYnBY */
 162
 163        /* DUART - UART2 */
 164        {5,  0, 1, 0, 2}, /* UART2_SOUT */
 165        {5,  2, 1, 0, 1}, /* UART2_RTS */
 166        {5,  3, 2, 0, 2}, /* UART2_SIN */
 167        {5,  1, 2, 0, 3}, /* UART2_CTS */
 168
 169        /* UCC5 - UART3 */
 170        {3,  0, 1, 0, 1}, /* UART3_TX */
 171        {3,  4, 1, 0, 1}, /* UART3_RTS */
 172        {3,  6, 2, 0, 1}, /* UART3_RX */
 173        {3, 12, 2, 0, 0}, /* UART3_CTS */
 174        {3, 13, 2, 0, 0}, /* UCC5_CD */
 175
 176        /* UCC6 - UART4 */
 177        {3, 14, 1, 0, 1}, /* UART4_TX */
 178        {3, 18, 1, 0, 1}, /* UART4_RTS */
 179        {3, 20, 2, 0, 1}, /* UART4_RX */
 180        {3, 26, 2, 0, 0}, /* UART4_CTS */
 181        {3, 27, 2, 0, 0}, /* UCC6_CD */
 182
 183        /* Fujitsu MB86277 (MINT) graphics controller */
 184        {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
 185        {1,  5, 1, 0, 0}, /* nXRST_GRAPHICS */
 186        {1,  7, 1, 0, 0}, /* LVDS_BKLT_CTR */
 187        {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
 188
 189        /* AD7843 ADC/Touchscreen controller */
 190        {4, 14, 1, 0, 0}, /* SPI_nCS0 */
 191        {4, 28, 3, 0, 3}, /* SPI_MOSI */
 192        {4, 29, 3, 0, 3}, /* SPI_MISO */
 193        {4, 30, 3, 0, 3}, /* SPI_CLK */
 194
 195        /* Freescale QUICC Engine USB Host Controller (FHCI) */
 196        {1,  2, 1, 0, 3}, /* USBOE */
 197        {1,  3, 1, 0, 3}, /* USBTP */
 198        {1,  8, 1, 0, 1}, /* USBTN */
 199        {1,  9, 2, 1, 3}, /* USBRP */
 200        {1, 10, 2, 0, 3}, /* USBRXD */
 201        {1, 11, 2, 1, 3}, /* USBRN */
 202        {2, 20, 2, 0, 1}, /* CLK21 */
 203        {4, 20, 1, 0, 0}, /* SPEED */
 204        {4, 21, 1, 0, 0}, /* SUSPND */
 205
 206        /* END of table */
 207        {0,  0, 0, 0, QE_IOP_TAB_END},
 208};
 209
 210int board_early_init_f(void)
 211{
 212        return 0;
 213}
 214
 215int board_early_init_r(void)
 216{
 217        void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
 218        u32 val;
 219
 220        /*
 221         * Because of errata in the UCCs, we have to write to the reserved
 222         * registers to slow the clocks down.
 223         */
 224        val = in_be32(reg);
 225        /* UCC1 */
 226        val |= 0x00003000;
 227        /* UCC2 */
 228        val |= 0x0c000000;
 229        out_be32(reg, val);
 230
 231        return 0;
 232}
 233
 234int fixed_sdram(void)
 235{
 236        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 237        u32 msize = 0;
 238        u32 ddr_size;
 239        u32 ddr_size_log2;
 240
 241        msize = CONFIG_SYS_DDR_SIZE;
 242        for (ddr_size = msize << 20, ddr_size_log2 = 0;
 243             (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 244                if (ddr_size & 1)
 245                        return -1;
 246        }
 247
 248        im->sysconf.ddrlaw[0].ar =
 249            LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 250
 251        im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
 252        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 253        im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 254        im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 255        im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 256        im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 257        im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 258        im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 259        im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 260        im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 261        im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 262        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 263        udelay(200);
 264        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 265
 266        return msize;
 267}
 268
 269phys_size_t initdram(int board_type)
 270{
 271#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 272        extern void ddr_enable_ecc(unsigned int dram_size);
 273#endif
 274        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 275        u32 msize = 0;
 276
 277        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 278                return -1;
 279
 280        /* DDR SDRAM - Main SODIMM */
 281        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 282        msize = fixed_sdram();
 283
 284#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 285        /*
 286         * Initialize DDR ECC byte
 287         */
 288        ddr_enable_ecc(msize * 1024 * 1024);
 289#endif
 290
 291        /* return total bus SDRAM size(bytes)  -- DDR */
 292        return (msize * 1024 * 1024);
 293}
 294
 295int checkboard(void)
 296{
 297        puts("Board: Freescale/Logic MPC8360ERDK\n");
 298        return 0;
 299}
 300
 301static struct pci_region pci_regions[] = {
 302        {
 303                .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
 304                .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
 305                .size = CONFIG_SYS_PCI1_MEM_SIZE,
 306                .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
 307        },
 308        {
 309                .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
 310                .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
 311                .size = CONFIG_SYS_PCI1_MMIO_SIZE,
 312                .flags = PCI_REGION_MEM,
 313        },
 314        {
 315                .bus_start = CONFIG_SYS_PCI1_IO_BASE,
 316                .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
 317                .size = CONFIG_SYS_PCI1_IO_SIZE,
 318                .flags = PCI_REGION_IO,
 319        },
 320};
 321
 322void pci_init_board(void)
 323{
 324        volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 325        volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 326        volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 327        struct pci_region *reg[] = { pci_regions, };
 328
 329#if defined(PCI_33M)
 330        clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
 331                    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
 332        printf("PCI clock is 33MHz\n");
 333#else
 334        clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
 335        printf("PCI clock is 66MHz\n");
 336#endif
 337
 338        udelay(2000);
 339
 340        /* Configure PCI Local Access Windows */
 341        pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 342        pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
 343
 344        pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 345        pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 346
 347        mpc83xx_pci_init(1, reg, 0);
 348}
 349
 350#if defined(CONFIG_OF_BOARD_SETUP)
 351void ft_board_setup(void *blob, bd_t *bd)
 352{
 353        ft_cpu_setup(blob, bd);
 354        ft_pci_setup(blob, bd);
 355}
 356#endif
 357