uboot/board/freescale/p1_p2_rdb/p1_p2_rdb.c
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   1/*
   2 * Copyright 2009 Freescale Semiconductor, Inc.
   3 *
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22
  23#include <common.h>
  24#include <command.h>
  25#include <asm/processor.h>
  26#include <asm/mmu.h>
  27#include <asm/cache.h>
  28#include <asm/immap_85xx.h>
  29#include <asm/io.h>
  30#include <miiphy.h>
  31#include <libfdt.h>
  32#include <fdt_support.h>
  33#include <tsec.h>
  34#include <vsc7385.h>
  35#include <netdev.h>
  36
  37DECLARE_GLOBAL_DATA_PTR;
  38
  39#define VSC7385_RST_SET         0x00080000
  40#define SLIC_RST_SET            0x00040000
  41#define SGMII_PHY_RST_SET       0x00020000
  42#define PCIE_RST_SET            0x00010000
  43#define RGMII_PHY_RST_SET       0x02000000
  44
  45#define USB_RST_CLR             0x04000000
  46
  47#define GPIO_DIR                0x060f0000
  48
  49#define BOARD_PERI_RST_SET      VSC7385_RST_SET | SLIC_RST_SET | \
  50                                SGMII_PHY_RST_SET | PCIE_RST_SET | \
  51                                RGMII_PHY_RST_SET
  52
  53#define SYSCLK_MASK     0x00200000
  54#define BOARDREV_MASK   0x10100000
  55#define BOARDREV_B      0x10100000
  56#define BOARDREV_C      0x00100000
  57
  58#define SYSCLK_66       66666666
  59#define SYSCLK_50       50000000
  60#define SYSCLK_100      100000000
  61
  62unsigned long get_board_sys_clk(ulong dummy)
  63{
  64        volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  65        u32 val_gpdat, sysclk_gpio, board_rev_gpio;
  66
  67        val_gpdat = pgpio->gpdat;
  68        sysclk_gpio = val_gpdat & SYSCLK_MASK;
  69        board_rev_gpio = val_gpdat & BOARDREV_MASK;
  70        if (board_rev_gpio == BOARDREV_C) {
  71                if(sysclk_gpio == 0)
  72                        return SYSCLK_66;
  73                else
  74                        return SYSCLK_100;
  75        } else if (board_rev_gpio == BOARDREV_B) {
  76                if(sysclk_gpio == 0)
  77                        return SYSCLK_66;
  78                else
  79                        return SYSCLK_50;
  80        }
  81        return 0;
  82}
  83
  84#ifdef CONFIG_MMC
  85int board_early_init_f (void)
  86{
  87        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  88
  89        setbits_be32(&gur->pmuxcr,
  90                        (MPC85xx_PMUXCR_SDHC_CD |
  91                         MPC85xx_PMUXCR_SDHC_WP));
  92        return 0;
  93}
  94#endif
  95
  96int checkboard (void)
  97{
  98        u32 val_gpdat, board_rev_gpio;
  99        volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 100        char board_rev = 0;
 101        struct cpu_type *cpu;
 102
 103        val_gpdat = pgpio->gpdat;
 104        board_rev_gpio = val_gpdat & BOARDREV_MASK;
 105        if (board_rev_gpio == BOARDREV_C)
 106                board_rev = 'C';
 107        else if (board_rev_gpio == BOARDREV_B)
 108                board_rev = 'B';
 109        else
 110                panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
 111
 112        cpu = gd->cpu;
 113        printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
 114        setbits_be32(&pgpio->gpdir, GPIO_DIR);
 115
 116/*
 117 * Bringing the following peripherals out of reset via GPIOs
 118 * 0 = reset and 1 = out of reset
 119 * GPIO12 - Reset to Ethernet Switch
 120 * GPIO13 - Reset to SLIC/SLAC devices
 121 * GPIO14 - Reset to SGMII_PHY_N
 122 * GPIO15 - Reset to PCIe slots
 123 * GPIO6  - Reset to RGMII PHY
 124 * GPIO5  - Reset to USB3300 devices 1 = reset and 0 = out of reset
 125 */
 126        clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
 127
 128        return 0;
 129}
 130
 131int board_early_init_r(void)
 132{
 133        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 134        const u8 flash_esel = 2;
 135
 136        /*
 137         * Remap Boot flash region to caching-inhibited
 138         * so that flash can be erased properly.
 139         */
 140
 141        /* Flush d-cache and invalidate i-cache of any FLASH data */
 142        flush_dcache();
 143        invalidate_icache();
 144
 145        /* invalidate existing TLB entry for flash */
 146        disable_tlb(flash_esel);
 147
 148        set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 149                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 150                        0, flash_esel, BOOKE_PAGESZ_16M, 1);
 151        return 0;
 152}
 153
 154
 155#ifdef CONFIG_TSEC_ENET
 156int board_eth_init(bd_t *bis)
 157{
 158        struct tsec_info_struct tsec_info[4];
 159        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 160        int num = 0;
 161        char *tmp;
 162        unsigned int vscfw_addr;
 163
 164#ifdef CONFIG_TSEC1
 165        SET_STD_TSEC_INFO(tsec_info[num], 1);
 166        num++;
 167#endif
 168#ifdef CONFIG_TSEC2
 169        SET_STD_TSEC_INFO(tsec_info[num], 2);
 170        num++;
 171#endif
 172#ifdef CONFIG_TSEC3
 173        SET_STD_TSEC_INFO(tsec_info[num], 3);
 174        if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 175                tsec_info[num].flags |= TSEC_SGMII;
 176        num++;
 177#endif
 178        if (!num) {
 179                printf("No TSECs initialized\n");
 180                return 0;
 181        }
 182#ifdef CONFIG_VSC7385_ENET
 183/* If a VSC7385 microcode image is present, then upload it. */
 184        if ((tmp = getenv ("vscfw_addr")) != NULL) {
 185                vscfw_addr = simple_strtoul (tmp, NULL, 16);
 186                printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
 187                if (vsc7385_upload_firmware((void *) vscfw_addr,
 188                                        CONFIG_VSC7385_IMAGE_SIZE))
 189                        puts("Failure uploading VSC7385 microcode.\n");
 190        } else
 191                puts("No address specified for VSC7385 microcode.\n");
 192#endif
 193
 194        tsec_eth_init(bis, tsec_info, num);
 195
 196        return pci_eth_init(bis);
 197}
 198#endif
 199
 200#if defined(CONFIG_OF_BOARD_SETUP)
 201void ft_board_setup(void *blob, bd_t *bd)
 202{
 203        phys_addr_t base;
 204        phys_size_t size;
 205
 206        ft_cpu_setup(blob, bd);
 207
 208        base = getenv_bootm_low();
 209        size = getenv_bootm_size();
 210
 211        fdt_fixup_memory(blob, (u64)base, (u64)size);
 212}
 213#endif
 214
 215#ifdef CONFIG_MP
 216extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 217
 218void board_lmb_reserve(struct lmb *lmb)
 219{
 220        cpu_mp_lmb_reserve(lmb);
 221}
 222#endif
 223