LXR uboot/board/inka4x0/inka4x0.c

   1/*
   2 * (C) Copyright 2008-2009
   3 * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
   4 *
   5 * (C) Copyright 2009
   6 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   7 *
   8 * (C) Copyright 2004
   9 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  10 *
  11 * (C) Copyright 2004
  12 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  13 *
  14 * (C) Copyright 2003-2004
  15 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  16 *
  17 * See file CREDITS for list of people who contributed to this
  18 * project.
  19 *
  20 * This program is free software; you can redistribute it and/or
  21 * modify it under the terms of the GNU General Public License as
  22 * published by the Free Software Foundation; either version 2 of
  23 * the License, or (at your option) any later version.
  24 *
  25 * This program is distributed in the hope that it will be useful,
  26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28 * GNU General Public License for more details.
  29 *
  30 * You should have received a copy of the GNU General Public License
  31 * along with this program; if not, write to the Free Software
  32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33 * MA 02111-1307 USA
  34 */
  35
  36#include <asm/io.h>
  37#include <common.h>
  38#include <mpc5xxx.h>
  39#include <pci.h>
  40
  41#if defined(CONFIG_DDR_MT46V16M16)
  42#include "mt46v16m16-75.h"
  43#elif defined(CONFIG_SDR_MT48LC16M16A2)
  44#include "mt48lc16m16a2-75.h"
  45#elif defined(CONFIG_DDR_MT46V32M16)
  46#include "mt46v32m16.h"
  47#elif defined(CONFIG_DDR_HYB25D512160BF)
  48#include "hyb25d512160bf.h"
  49#elif defined(CONFIG_DDR_K4H511638C)
  50#include "k4h511638c.h"
  51#else
  52#error "INKA4x0 SDRAM: invalid chip type specified!"
  53#endif
  54
  55#ifndef CONFIG_SYS_RAMBOOT
  56static void sdram_start (int hi_addr)
  57{
  58        volatile struct mpc5xxx_sdram *sdram =
  59                (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  60        long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  61
  62        /* unlock mode register */
  63        out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
  64
  65        /* precharge all banks */
  66        out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
  67
  68#if SDRAM_DDR
  69        /* set mode register: extended mode */
  70        out_be32(&sdram->mode, SDRAM_EMODE);
  71
  72        /* set mode register: reset DLL */
  73        out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
  74#endif
  75
  76        /* precharge all banks */
  77        out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
  78
  79        /* auto refresh */
  80        out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
  81
  82        /* set mode register */
  83        out_be32(&sdram->mode, SDRAM_MODE);
  84
  85        /* normal operation */
  86        out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
  87}
  88#endif
  89
  90/*
  91 * ATTENTION: Although partially referenced initdram does NOT make real use
  92 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  93 *            is something else than 0x00000000.
  94 */
  95
  96phys_size_t initdram (int board_type)
  97{
  98        volatile struct mpc5xxx_mmap_ctl *mm =
  99                (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
 100        volatile struct mpc5xxx_cdm     *cdm =
 101                (struct mpc5xxx_cdm *)      MPC5XXX_CDM;
 102        volatile struct mpc5xxx_sdram *sdram =
 103                (struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
 104        ulong dramsize = 0;
 105#ifndef CONFIG_SYS_RAMBOOT
 106        long test1, test2;
 107
 108        /* setup SDRAM chip selects */
 109        out_be32(&mm->sdram0, 0x0000001c);      /* 512MB at 0x0 */
 110        out_be32(&mm->sdram1, 0x40000000);      /* disabled */
 111
 112        /* setup config registers */
 113        out_be32(&sdram->config1, SDRAM_CONFIG1);
 114        out_be32(&sdram->config2, SDRAM_CONFIG2);
 115
 116#if SDRAM_DDR
 117        /* set tap delay */
 118        out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
 119#endif
 120
 121        /* find RAM size using SDRAM CS0 only */
 122        sdram_start(0);
 123        test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 124        sdram_start(1);
 125        test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 126        if (test1 > test2) {
 127                sdram_start(0);
 128                dramsize = test1;
 129        } else {
 130                dramsize = test2;
 131        }
 132
 133        /* memory smaller than 1MB is impossible */
 134        if (dramsize < (1 << 20)) {
 135                dramsize = 0;
 136        }
 137
 138        /* set SDRAM CS0 size according to the amount of RAM found */
 139        if (dramsize > 0) {
 140                out_be32(&mm->sdram0, 0x13 +
 141                         __builtin_ffs(dramsize >> 20) - 1);
 142        } else {
 143                out_be32(&mm->sdram0, 0); /* disabled */
 144        }
 145
 146        out_be32(&mm->sdram1, dramsize); /* disabled */
 147#else /* CONFIG_SYS_RAMBOOT */
 148
 149        /* retrieve size of memory connected to SDRAM CS0 */
 150        dramsize = in_be32(&mm->sdram0) & 0xFF;
 151        if (dramsize >= 0x13) {
 152                dramsize = (1 << (dramsize - 0x13)) << 20;
 153        } else {
 154                dramsize = 0;
 155        }
 156#endif /* CONFIG_SYS_RAMBOOT */
 157
 158        return dramsize;
 159}
 160
 161int checkboard (void)
 162{
 163        puts ("Board: INKA 4X0\n");
 164        return 0;
 165}
 166
 167void flash_preinit(void)
 168{
 169        volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
 170
 171        /*
 172         * Now, when we are in RAM, enable flash write
 173         * access for detection process.
 174         * Note that CS_BOOT (CS0) cannot be cleared when
 175         * executing in flash.
 176         */
 177        clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
 178}
 179
 180int misc_init_f (void)
 181{
 182        volatile struct mpc5xxx_gpio    *gpio    =
 183                (struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
 184        volatile struct mpc5xxx_wu_gpio *wu_gpio =
 185                (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 186        volatile struct mpc5xxx_gpt     *gpt;
 187        char tmp[10];
 188        int i, br;
 189
 190        i = getenv_r("brightness", tmp, sizeof(tmp));
 191        br = (i > 0)
 192                ? (int) simple_strtoul (tmp, NULL, 10)
 193                : CONFIG_SYS_BRIGHTNESS;
 194        if (br > 255)
 195                br = 255;
 196
 197        /* Initialize GPIO output pins.
 198         */
 199        /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
 200        for (i = 0; i <= 5; i++) {
 201                gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
 202                out_be32(&gpt->emsr, 0x34);
 203        }
 204
 205        /* Configure GPT7 as PWM timer, 1kHz, no ints. */
 206        gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
 207        out_be32(&gpt->emsr,  0);               /* Disable */
 208        out_be32(&gpt->cir,   0x020000fe);
 209        out_be32(&gpt->pwmcr, (br << 16));
 210        out_be32(&gpt->emsr,  0x3);             /* Enable PWM mode and start */
 211
 212        /* Configure PSC3_6,7 as GPIO output */
 213        setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
 214                                          MPC5XXX_GPIO_SIMPLE_PSC3_7);
 215        setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
 216                                          MPC5XXX_GPIO_SIMPLE_PSC3_7);
 217
 218        /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
 219        setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
 220                                     MPC5XXX_GPIO_WKUP_7 |
 221                                     MPC5XXX_GPIO_WKUP_PSC3_9);
 222        setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
 223                                     MPC5XXX_GPIO_WKUP_7 |
 224                                     MPC5XXX_GPIO_WKUP_PSC3_9);
 225
 226        /* Set LR mirror bit because it is low-active */
 227        setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);
 228
 229        /* Reset Coral-P graphics controller */
 230        setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);
 231
 232        /* Enable display backlight */
 233        clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
 234        setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
 235        setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
 236        setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);
 237
 238        /*
 239         * Configure three wire serial interface to RTC (PSC1_4,
 240         * PSC2_4, PSC3_4, PSC3_5)
 241         */
 242        setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
 243                                     MPC5XXX_GPIO_WKUP_PSC2_4);
 244        setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
 245                                     MPC5XXX_GPIO_WKUP_PSC2_4);
 246        clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
 247        clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
 248                                     MPC5XXX_GPIO_SINT_PSC3_5);
 249        setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
 250                                     MPC5XXX_GPIO_SINT_PSC3_5);
 251        setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
 252        clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);
 253
 254        return 0;
 255}
 256
 257#ifdef  CONFIG_PCI
 258static struct pci_controller hose;
 259
 260extern void pci_mpc5xxx_init(struct pci_controller *);
 261
 262void pci_init_board(void)
 263{
 264        pci_mpc5xxx_init(&hose);
 265}
 266#endif
 267