LXR uboot/board/sbc8560/sbc8560.c

   1/*
   2 * (C) Copyright 2003,Motorola Inc.
   3 * Xianghua Xiao, (X.Xiao@motorola.com)
   4 *
   5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6 *
   7 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
   8 * Added support for Wind River SBC8560 board
   9 *
  10 * See file CREDITS for list of people who contributed to this
  11 * project.
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License as
  15 * published by the Free Software Foundation; either version 2 of
  16 * the License, or (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 * MA 02111-1307 USA
  27 */
  28
  29
  30#include <common.h>
  31#include <asm/processor.h>
  32#include <asm/mmu.h>
  33#include <asm/immap_85xx.h>
  34#include <asm/fsl_ddr_sdram.h>
  35#include <ioports.h>
  36#include <spd_sdram.h>
  37#include <miiphy.h>
  38#include <libfdt.h>
  39#include <fdt_support.h>
  40
  41long int fixed_sdram (void);
  42
  43/*
  44 * I/O Port configuration table
  45 *
  46 * if conf is 1, then that port pin will be configured at boot time
  47 * according to the five values podr/pdir/ppar/psor/pdat for that entry
  48 */
  49
  50const iop_conf_t iop_conf_tab[4][32] = {
  51
  52    /* Port A configuration */
  53    {   /*            conf ppar psor pdir podr pdat */
  54        /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  55        /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  56        /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  57        /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  58        /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  59        /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  60        /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  61        /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  62        /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  63        /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  64        /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  65        /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  66        /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  67        /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  68        /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  69        /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  70        /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  71        /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  72        /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  73        /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  74        /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  75        /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  76        /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  77        /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  78        /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  79        /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  80        /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  81        /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  82        /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  83        /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  84        /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  85        /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  86    },
  87
  88    /* Port B configuration */
  89    {   /*            conf ppar psor pdir podr pdat */
  90        /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  91        /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  92        /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  93        /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  94        /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  95        /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  96        /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  97        /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
  98        /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
  99        /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
 100        /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
 101        /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 102        /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 103        /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 104        /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
 105        /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
 106        /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
 107        /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
 108        /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
 109        /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 110        /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 111        /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 112        /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 113        /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 114        /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 115        /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 116        /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 117        /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 118        /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 119        /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 120        /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 121        /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 122    },
 123
 124    /* Port C */
 125    {   /*            conf ppar psor pdir podr pdat */
 126        /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 127        /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 128        /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 129        /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 130        /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 131        /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 132        /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 133        /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 134        /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 135        /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 136        /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 137        /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 138        /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 139        /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 140        /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 141        /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 142        /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 143        /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 144        /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 145        /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 146        /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 147        /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 148        /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 149        /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 150        /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 151        /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 152        /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 153        /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 154        /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 155        /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 156        /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 157        /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 158    },
 159
 160    /* Port D */
 161    {   /*            conf ppar psor pdir podr pdat */
 162        /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 163        /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 164        /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
 165        /* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
 166        /* PD27 */ {   1,   1,   1,   1,   0,   0   }, /* SCC2 TxD */
 167        /* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
 168        /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 169        /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 170        /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 171        /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 172        /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 173        /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 174        /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 175        /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 176        /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 177        /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 178        /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 179        /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 180        /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 181        /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 182        /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 183        /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 184        /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 185        /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 186        /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 187        /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 188        /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 189        /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 190        /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 191        /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 192        /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 193        /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 194    }
 195};
 196
 197int board_early_init_f (void)
 198{
 199#if defined(CONFIG_PCI)
 200    volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
 201
 202    pci->peer &= 0xfffffffdf; /* disable master abort */
 203#endif
 204        return 0;
 205}
 206
 207void reset_phy (void)
 208{
 209#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
 210        volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
 211#endif
 212        /* reset Giga bit Ethernet port if needed here */
 213
 214        /* reset the CPM FEC port */
 215#if (CONFIG_ETHER_INDEX == 2)
 216        bcsr[0] &= ~0x20;
 217        udelay(2);
 218        bcsr[0] |= 0x20;
 219        udelay(1000);
 220#elif (CONFIG_ETHER_INDEX == 3)
 221        bcsr[0] &= ~0x10;
 222        udelay(2);
 223        bcsr[0] |= 0x10;
 224        udelay(1000);
 225#endif
 226#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
 227        /* reset PHY */
 228        miiphy_reset("FCC1 ETHERNET", 0x0);
 229
 230        /* change PHY address to 0x02 */
 231        bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
 232
 233        bb_miiphy_write(NULL, 0x02, PHY_BMCR,
 234                        PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 235#endif /* CONFIG_MII */
 236}
 237
 238int checkboard (void)
 239{
 240        sys_info_t sysinfo;
 241        char buf[32];
 242
 243        get_sys_info (&sysinfo);
 244
 245#ifdef CONFIG_SBC8560
 246        printf ("Board: Wind River SBC8560 Board\n");
 247#else
 248        printf ("Board: Wind River SBC8540 Board\n");
 249#endif
 250        printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
 251        printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
 252        printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
 253        if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
 254                || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
 255                printf ("\tLBC: %s MHz\n",
 256                        strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
 257        } else {
 258                printf("\tLBC: unknown\n");
 259        }
 260        printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
 261        printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
 262        return (0);
 263}
 264
 265
 266phys_size_t initdram (int board_type)
 267{
 268        long dram_size = 0;
 269
 270#if 0
 271#if !defined(CONFIG_RAM_AS_FLASH)
 272        volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 273        sys_info_t sysinfo;
 274        uint temp_lbcdll = 0;
 275#endif
 276#endif /* 0 */
 277#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
 278        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 279#endif
 280#if defined(CONFIG_DDR_DLL)
 281        uint temp_ddrdll = 0;
 282
 283        /* Work around to stabilize DDR DLL */
 284        temp_ddrdll = gur->ddrdllcr;
 285        gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
 286        asm("sync;isync;msync");
 287#endif
 288
 289#if defined(CONFIG_SPD_EEPROM)
 290        dram_size = fsl_ddr_sdram();
 291        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 292        dram_size *= 0x100000;
 293#else
 294        dram_size = fixed_sdram ();
 295#endif
 296
 297#if 0
 298#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
 299        get_sys_info(&sysinfo);
 300        /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
 301        if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
 302                lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
 303        } else {
 304#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
 305                lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
 306#endif
 307                lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
 308                udelay(200);
 309                temp_lbcdll = gur->lbcdllcr;
 310                gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 311                asm("sync;isync;msync");
 312        }
 313        lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
 314        lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 315        lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 316        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 317        asm("sync");
 318        (unsigned int) * (ulong *)0 = 0x000000ff;
 319        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 320        asm("sync");
 321        (unsigned int) * (ulong *)0 = 0x000000ff;
 322        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 323        asm("sync");
 324        (unsigned int) * (ulong *)0 = 0x000000ff;
 325        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 326        asm("sync");
 327        (unsigned int) * (ulong *)0 = 0x000000ff;
 328        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 329        asm("sync");
 330        lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 331        asm("sync");
 332        lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 333        asm("sync");
 334#endif
 335#endif
 336
 337#if defined(CONFIG_DDR_ECC)
 338        {
 339                /* Initialize all of memory for ECC, then
 340                 * enable errors */
 341                volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 342
 343                dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
 344
 345                /* Enable errors for ECC */
 346                ddr->err_disable = 0x00000000;
 347                asm("sync;isync;msync");
 348        }
 349#endif
 350
 351        return dram_size;
 352}
 353
 354
 355#if defined(CONFIG_SYS_DRAM_TEST)
 356int testdram (void)
 357{
 358        uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
 359        uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 360        uint *p;
 361
 362        printf("SDRAM test phase 1:\n");
 363        for (p = pstart; p < pend; p++)
 364                *p = 0xaaaaaaaa;
 365
 366        for (p = pstart; p < pend; p++) {
 367                if (*p != 0xaaaaaaaa) {
 368                        printf ("SDRAM test fails at: %08x\n", (uint) p);
 369                        return 1;
 370                }
 371        }
 372
 373        printf("SDRAM test phase 2:\n");
 374        for (p = pstart; p < pend; p++)
 375                *p = 0x55555555;
 376
 377        for (p = pstart; p < pend; p++) {
 378                if (*p != 0x55555555) {
 379                        printf ("SDRAM test fails at: %08x\n", (uint) p);
 380                        return 1;
 381                }
 382        }
 383
 384        printf("SDRAM test passed.\n");
 385        return 0;
 386}
 387#endif
 388
 389#if !defined(CONFIG_SPD_EEPROM)
 390/*************************************************************************
 391 *  fixed sdram init -- doesn't use serial presence detect.
 392 ************************************************************************/
 393long int fixed_sdram (void)
 394{
 395
 396#define CONFIG_SYS_DDR_CONTROL 0xc2000000
 397
 398  #ifndef CONFIG_SYS_RAMBOOT
 399        volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 400
 401#if (CONFIG_SYS_SDRAM_SIZE == 512)
 402        ddr->cs0_bnds           = 0x0000000f;
 403#else
 404        ddr->cs0_bnds           = 0x00000007;
 405#endif
 406        ddr->cs1_bnds           = 0x0010001f;
 407        ddr->cs2_bnds           = 0x00000000;
 408        ddr->cs3_bnds           = 0x00000000;
 409        ddr->cs0_config         = 0x80000102;
 410        ddr->cs1_config         = 0x80000102;
 411        ddr->cs2_config         = 0x00000000;
 412        ddr->cs3_config         = 0x00000000;
 413        ddr->timing_cfg_1       = 0x37334321;
 414        ddr->timing_cfg_2       = 0x00000800;
 415        ddr->sdram_cfg          = 0x42000000;
 416        ddr->sdram_mode         = 0x00000022;
 417        ddr->sdram_interval     = 0x05200100;
 418        ddr->err_sbe            = 0x00ff0000;
 419    #if defined (CONFIG_DDR_ECC)
 420        ddr->err_disable = 0x0000000D;
 421    #endif
 422        asm("sync;isync;msync");
 423        udelay(500);
 424    #if defined (CONFIG_DDR_ECC)
 425        /* Enable ECC checking */
 426        ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 427    #else
 428        ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 429    #endif
 430        asm("sync; isync; msync");
 431        udelay(500);
 432  #endif
 433        return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 434}
 435#endif  /* !defined(CONFIG_SPD_EEPROM) */
 436
 437
 438#if defined(CONFIG_OF_BOARD_SETUP)
 439void
 440ft_board_setup(void *blob, bd_t *bd)
 441{
 442        int node, tmp[2];
 443#ifdef CONFIG_PCI
 444        const char *path;
 445#endif
 446
 447        ft_cpu_setup(blob, bd);
 448
 449        node = fdt_path_offset(blob, "/aliases");
 450        tmp[0] = 0;
 451        if (node >= 0) {
 452#ifdef CONFIG_PCI
 453                path = fdt_getprop(blob, node, "pci0", NULL);
 454                if (path) {
 455                        tmp[1] = hose.last_busno - hose.first_busno;
 456                        do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 457                }
 458#endif
 459        }
 460}
 461#endif
 462