LXR uboot/board/spd8xx/spd8xx.c

   1/*
   2 * (C) Copyright 2000
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <common.h>
  26#include <mpc8xx.h>
  27#include <commproc.h>
  28
  29/* ------------------------------------------------------------------------- */
  30
  31static long int dram_size (long int, long int *, long int);
  32
  33/* ------------------------------------------------------------------------- */
  34
  35#define _NOT_USED_      0xFFFFFFFF
  36
  37const uint sharc_table[] = {
  38        /*
  39         * Single Read. (Offset 0 in UPM RAM)
  40         */
  41        0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
  42        0xFFFFEC05,             /* last */
  43        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  44        /*
  45         * Burst Read. (Offset 8 in UPM RAM)
  46         */
  47        /* last */
  48        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  49        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  50        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  51        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  52        /*
  53         * Single Write. (Offset 18 in UPM RAM)
  54         */
  55        0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
  56        0xFFFFEC05,             /* last */
  57        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  58        /*
  59         * Burst Write. (Offset 20 in UPM RAM)
  60         */
  61        /* last */
  62        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  63        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  64        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  65        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  66        /*
  67         * Refresh  (Offset 30 in UPM RAM)
  68         */
  69        /* last */
  70        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  71        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  72        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73        /*
  74         * Exception. (Offset 3c in UPM RAM)
  75         */
  76        0x7FFFFC07,             /* last */
  77        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  78};
  79
  80
  81const uint sdram_table[] = {
  82        /*
  83         * Single Read. (Offset 0 in UPM RAM)
  84         */
  85        0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
  86        0x1FF77C47,             /* last */
  87        /*
  88         * SDRAM Initialization (offset 5 in UPM RAM)
  89         *
  90         * This is no UPM entry point. The following definition uses
  91         * the remaining space to establish an initialization
  92         * sequence, which is executed by a RUN command.
  93         *
  94         */
  95        0x1FF77C35, 0xEFEABC34, 0x1FB57C35,     /* last */
  96        /*
  97         * Burst Read. (Offset 8 in UPM RAM)
  98         */
  99        0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
 100        0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
 101        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 102        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 103        /*
 104         * Single Write. (Offset 18 in UPM RAM)
 105         */
 106        0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
 107        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 108        /*
 109         * Burst Write. (Offset 20 in UPM RAM)
 110         */
 111        0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
 112        0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,     /* last */
 113        _NOT_USED_,
 114        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 115        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 116        /*
 117         * Refresh  (Offset 30 in UPM RAM)
 118         */
 119        0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
 120        0xFFFFFC84, 0xFFFFFC07, /* last */
 121        _NOT_USED_, _NOT_USED_,
 122        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 123        /*
 124         * Exception. (Offset 3c in UPM RAM)
 125         */
 126        0x7FFFFC07,             /* last */
 127        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 128};
 129
 130/* ------------------------------------------------------------------------- */
 131
 132
 133/*
 134 * Check Board Identity:
 135 *
 136 */
 137
 138int checkboard (void)
 139{
 140        puts ("Board: SPD823TS\n");
 141        return (0);
 142}
 143
 144/* ------------------------------------------------------------------------- */
 145
 146phys_size_t initdram (int board_type)
 147{
 148        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 149        volatile memctl8xx_t *memctl = &immap->im_memctl;
 150        long int size_b0;
 151
 152#if 0
 153        /*
 154         * Map controller bank 2 to the SRAM bank at preliminary address.
 155         */
 156        memctl->memc_or2 = CONFIG_SYS_OR2;
 157        memctl->memc_br2 = CONFIG_SYS_BR2;
 158#endif
 159
 160        /*
 161         * Map controller bank 4 to the PER8 bank.
 162         */
 163        memctl->memc_or4 = CONFIG_SYS_OR4;
 164        memctl->memc_br4 = CONFIG_SYS_BR4;
 165
 166#if 0
 167        /* Configure SHARC at UMA */
 168        upmconfig (UPMA, (uint *) sharc_table,
 169                   sizeof (sharc_table) / sizeof (uint));
 170        /* Map controller bank 5 to the SHARC */
 171        memctl->memc_or5 = CONFIG_SYS_OR5;
 172        memctl->memc_br5 = CONFIG_SYS_BR5;
 173#endif
 174
 175        memctl->memc_mamr = 0x00001000;
 176
 177        /* Configure SDRAM at UMB */
 178        upmconfig (UPMB, (uint *) sdram_table,
 179                   sizeof (sdram_table) / sizeof (uint));
 180
 181        memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
 182
 183        memctl->memc_mar = 0x00000088;
 184
 185        /*
 186         * Map controller bank 3 to the SDRAM bank at preliminary address.
 187         */
 188        memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 189        memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 190
 191        memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;       /* refresh not enabled yet */
 192
 193        udelay (200);
 194        memctl->memc_mcr = 0x80806105;
 195        udelay (1);
 196        memctl->memc_mcr = 0x80806130;
 197        udelay (1);
 198        memctl->memc_mcr = 0x80806130;
 199        udelay (1);
 200        memctl->memc_mcr = 0x80806106;
 201
 202        memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
 203
 204        /*
 205         * Check Bank 0 Memory Size for re-configuration
 206         */
 207        size_b0 =
 208                dram_size (CONFIG_SYS_MBMR_8COL, SDRAM_BASE3_PRELIM,
 209                           SDRAM_MAX_SIZE);
 210
 211        memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
 212
 213        return (size_b0);
 214}
 215
 216/* ------------------------------------------------------------------------- */
 217
 218/*
 219 * Check memory range for valid RAM. A simple memory test determines
 220 * the actually available RAM size between addresses `base' and
 221 * `base + maxsize'. Some (not all) hardware errors are detected:
 222 * - short between address lines
 223 * - short between data lines
 224 */
 225
 226static long int dram_size (long int mamr_value, long int *base,
 227                           long int maxsize)
 228{
 229        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 230        volatile memctl8xx_t *memctl = &immap->im_memctl;
 231
 232        memctl->memc_mbmr = mamr_value;
 233
 234        return (get_ram_size (base, maxsize));
 235}
 236
 237/* ------------------------------------------------------------------------- */
 238
 239void reset_phy (void)
 240{
 241        immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 242        ushort sreg;
 243
 244        /* Configure extra port pins for NS DP83843 PHY */
 245        immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
 246
 247        sreg = immr->im_ioport.iop_padir;
 248        sreg |= PA_ENET_MDC;    /* Mgmt. Data Clock is Output */
 249        sreg &= ~(PA_ENET_MDIO);        /* Mgmt. Data I/O is bidirect. => Input */
 250        immr->im_ioport.iop_padir = sreg;
 251
 252        immr->im_ioport.iop_padat &= ~(PA_ENET_MDC);    /* set MDC = 0 */
 253
 254        /*
 255         * RESET in implemented by a positive pulse of at least 1 us
 256         * at the reset pin.
 257         *
 258         * Configure RESET pins for NS DP83843 PHY, and RESET chip.
 259         *
 260         * Note: The RESET pin is high active, but there is an
 261         *       inverter on the SPD823TS board...
 262         */
 263        immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
 264        immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
 265        /* assert RESET signal of PHY */
 266        immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
 267        udelay (10);
 268        /* de-assert RESET signal of PHY */
 269        immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
 270        udelay (10);
 271}
 272
 273/* ------------------------------------------------------------------------- */
 274
 275void ide_set_reset (int on)
 276{
 277        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 278
 279        /*
 280         * Configure PC for IDE Reset Pin
 281         */
 282        if (on) {               /* assert RESET */
 283                immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
 284        } else {                /* release RESET */
 285                immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
 286        }
 287
 288        /* program port pin as GPIO output */
 289        immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
 290        immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
 291        immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
 292}
 293
 294/* ------------------------------------------------------------------------- */
 295