1/* 2 * 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <common.h> 29#include <watchdog.h> 30#include <asm/immap.h> 31 32#if defined(CONFIG_CMD_NET) 33#include <config.h> 34#include <net.h> 35#include <asm/fec.h> 36#endif 37 38#ifdef CONFIG_MCF5301x 39void cpu_init_f(void) 40{ 41 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 42 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 43 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 44 45 /* watchdog is enabled by default - disable the watchdog */ 46#ifndef CONFIG_WATCHDOG 47 /*wdog->cr = 0; */ 48#endif 49 50 scm1->mpr = 0x77777777; 51 scm1->pacra = 0; 52 scm1->pacrb = 0; 53 scm1->pacrc = 0; 54 scm1->pacrd = 0; 55 scm1->pacre = 0; 56 scm1->pacrf = 0; 57 scm1->pacrg = 0; 58 59#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 60 && defined(CONFIG_SYS_CS0_CTRL)) 61 gpio->par_cs |= GPIO_PAR_CS0_CS0; 62 fbcs->csar0 = CONFIG_SYS_CS0_BASE; 63 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; 64 fbcs->csmr0 = CONFIG_SYS_CS0_MASK; 65#endif 66 67#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 68 && defined(CONFIG_SYS_CS1_CTRL)) 69 gpio->par_cs |= GPIO_PAR_CS1_CS1; 70 fbcs->csar1 = CONFIG_SYS_CS1_BASE; 71 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; 72 fbcs->csmr1 = CONFIG_SYS_CS1_MASK; 73#endif 74 75#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 76 && defined(CONFIG_SYS_CS2_CTRL)) 77 fbcs->csar2 = CONFIG_SYS_CS2_BASE; 78 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; 79 fbcs->csmr2 = CONFIG_SYS_CS2_MASK; 80#endif 81 82#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 83 && defined(CONFIG_SYS_CS3_CTRL)) 84 fbcs->csar3 = CONFIG_SYS_CS3_BASE; 85 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; 86 fbcs->csmr3 = CONFIG_SYS_CS3_MASK; 87#endif 88 89#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 90 && defined(CONFIG_SYS_CS4_CTRL)) 91 gpio->par_cs |= GPIO_PAR_CS4; 92 fbcs->csar4 = CONFIG_SYS_CS4_BASE; 93 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; 94 fbcs->csmr4 = CONFIG_SYS_CS4_MASK; 95#endif 96 97#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 98 && defined(CONFIG_SYS_CS5_CTRL)) 99 gpio->par_cs |= GPIO_PAR_CS5; 100 fbcs->csar5 = CONFIG_SYS_CS5_BASE; 101 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; 102 fbcs->csmr5 = CONFIG_SYS_CS5_MASK; 103#endif 104 105#ifdef CONFIG_FSL_I2C 106 gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL; 107#endif 108 109 icache_enable(); 110} 111 112/* initialize higher level parts of CPU like timers */ 113int cpu_init_r(void) 114{ 115#ifdef CONFIG_MCFFEC 116 volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; 117#endif 118#ifdef CONFIG_MCFRTC 119 volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); 120 volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended; 121 122 rtcex->gocu = CONFIG_SYS_RTC_CNT; 123 rtcex->gocl = CONFIG_SYS_RTC_SETUP; 124 125#endif 126#ifdef CONFIG_MCFFEC 127 if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) 128 ccm->misccr |= CCM_MISCCR_FECM; 129 else 130 ccm->misccr &= ~CCM_MISCCR_FECM; 131#endif 132 133 return (0); 134} 135 136void uart_port_conf(void) 137{ 138 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 139 140 /* Setup Ports: */ 141 switch (CONFIG_SYS_UART_PORT) { 142 case 0: 143 gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); 144 break; 145 case 1: 146#ifdef CONFIG_SYS_UART1_ALT1_GPIO 147 gpio->par_simp1h &= 148 ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK); 149 gpio->par_simp1h |= 150 (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD); 151#elif defined(CONFIG_SYS_UART1_ALT2_GPIO) 152 gpio->par_ssih &= 153 ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK); 154 gpio->par_ssih |= 155 (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD); 156#endif 157 break; 158 case 2: 159#ifdef CONFIG_SYS_UART2_PRI_GPIO 160 gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD); 161#elif defined(CONFIG_SYS_UART2_ALT1_GPIO) 162 gpio->par_dspih &= 163 ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK); 164 gpio->par_dspih |= 165 (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD); 166#elif defined(CONFIG_SYS_UART2_ALT2_GPIO) 167 gpio->par_feci2c &= 168 ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK); 169 gpio->par_feci2c |= 170 (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); 171#endif 172 break; 173 } 174} 175 176#if defined(CONFIG_CMD_NET) 177int fecpin_setclear(struct eth_device *dev, int setclear) 178{ 179 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 180 struct fec_info_s *info = (struct fec_info_s *)dev->priv; 181 182 if (setclear) { 183 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 184 gpio->par_fec |= 185 GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC; 186 gpio->par_feci2c |= 187 GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0; 188 } else { 189 gpio->par_fec |= 190 GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC; 191 gpio->par_feci2c |= 192 GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1; 193 } 194 } else { 195 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { 196 gpio->par_fec &= 197 ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); 198 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK; 199 } else { 200 gpio->par_fec &= 201 ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); 202 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK; 203 } 204 } 205 return 0; 206} 207#endif /* CONFIG_CMD_NET */ 208#endif /* CONFIG_MCF5301x */ 209 210#ifdef CONFIG_MCF532x 211void cpu_init_f(void) 212{ 213 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; 214 volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; 215 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 216 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; 217 volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; 218 219 /* watchdog is enabled by default - disable the watchdog */ 220#ifndef CONFIG_WATCHDOG 221 wdog->cr = 0; 222#endif 223 224 scm1->mpr0 = 0x77777777; 225 scm2->pacra = 0; 226 scm2->pacrb = 0; 227 scm2->pacrc = 0; 228 scm2->pacrd = 0; 229 scm2->pacre = 0; 230 scm2->pacrf = 0; 231 scm2->pacrg = 0; 232 scm1->pacrh = 0; 233 234 /* Port configuration */ 235 gpio->par_cs = 0; 236 237#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ 238 && defined(CONFIG_SYS_CS0_CTRL)) 239 fbcs->csar0 = CONFIG_SYS_CS0_BASE; 240 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; 241 fbcs->csmr0 = CONFIG_SYS_CS0_MASK; 242#endif 243 244#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ 245 && defined(CONFIG_SYS_CS1_CTRL)) 246 /* Latch chipselect */ 247 gpio->par_cs |= GPIO_PAR_CS1; 248 fbcs->csar1 = CONFIG_SYS_CS1_BASE; 249 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; 250 fbcs->csmr1 = CONFIG_SYS_CS1_MASK; 251#endif 252 253#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ 254 && defined(CONFIG_SYS_CS2_CTRL)) 255 gpio->par_cs |= GPIO_PAR_CS2; 256 fbcs->csar2 = CONFIG_SYS_CS2_BASE; 257 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; 258 fbcs->csmr2 = CONFIG_SYS_CS2_MASK; 259#endif 260 261#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ 262 && defined(CONFIG_SYS_CS3_CTRL)) 263 gpio->par_cs |= GPIO_PAR_CS3; 264 fbcs->csar3 = CONFIG_SYS_CS3_BASE; 265 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; 266 fbcs->csmr3 = CONFIG_SYS_CS3_MASK; 267#endif 268 269#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ 270 && defined(CONFIG_SYS_CS4_CTRL)) 271 gpio->par_cs |= GPIO_PAR_CS4; 272 fbcs->csar4 = CONFIG_SYS_CS4_BASE; 273 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; 274 fbcs->csmr4 = CONFIG_SYS_CS4_MASK; 275#endif 276 277#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ 278 && defined(CONFIG_SYS_CS5_CTRL)) 279 gpio->par_cs |= GPIO_PAR_CS5; 280 fbcs->csar5 = CONFIG_SYS_CS5_BASE; 281 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; 282 fbcs->csmr5 = CONFIG_SYS_CS5_MASK; 283#endif 284 285#ifdef CONFIG_FSL_I2C 286 gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; 287#endif 288 289 icache_enable(); 290} 291 292/* 293 * initialize higher level parts of CPU like timers 294 */ 295int cpu_init_r(void) 296{ 297 return (0); 298} 299 300void uart_port_conf(void) 301{ 302 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 303 304 /* Setup Ports: */ 305 switch (CONFIG_SYS_UART_PORT) { 306 case 0: 307 gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); 308 break; 309 case 1: 310 gpio->par_uart = 311 (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); 312 break; 313 case 2: 314 gpio->par_timer &= 0x0F; 315 gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); 316 break; 317 } 318} 319 320#if defined(CONFIG_CMD_NET) 321int fecpin_setclear(struct eth_device *dev, int setclear) 322{ 323 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 324 325 if (setclear) { 326 gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; 327 gpio->par_feci2c |= 328 GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; 329 } else { 330 gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); 331 gpio->par_feci2c &= 332 ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); 333 } 334 return 0; 335} 336#endif 337#endif /* CONFIG_MCF532x */ 338