1/* 2 * MPU Masks 3 */ 4 5#ifndef __BFIN_PERIPHERAL_MPU__ 6#define __BFIN_PERIPHERAL_MPU__ 7 8/* 9 * DMEM_CONTROL Register 10 */ 11 12/* ** Bit Positions */ 13#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */ 14#define DMCTL_ENDM_P ENDM_P /* "" (older define) */ 15#define ENDCPLB_P 0x01 /* Enable DCPLBS */ 16#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */ 17#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */ 18#define DMCTL_DMC0_P DMC0_P /* "" (older define) */ 19#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */ 20#define DMCTL_DMC1_P DMC1_P /* "" (older define) */ 21#define DCBS_P 0x04 /* L1 Data Cache Bank Select */ 22#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ 23#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ 24 25/* ** Masks */ 26#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */ 27#define ENDCPLB 0x00000002 /* Enable DCPLB */ 28#define ASRAM_BSRAM 0x00000000 29#define ACACHE_BSRAM 0x00000008 30#define ACACHE_BCACHE 0x0000000C 31#define DCBS 0x00000010 /* L1 Data Cache Bank Select */ 32#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ 33#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ 34 35/* IMEM_CONTROL Register */ 36/* ** Bit Positions */ 37#define ENIM_P 0x00 /* Enable L1 Code Memory */ 38#define IMCTL_ENIM_P 0x00 /* "" (older define) */ 39#define ENICPLB_P 0x01 /* Enable ICPLB */ 40#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ 41#define IMC_P 0x02 /* Enable */ 42#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */ 43#define ILOC0_P 0x03 /* Lock Way 0 */ 44#define ILOC1_P 0x04 /* Lock Way 1 */ 45#define ILOC2_P 0x05 /* Lock Way 2 */ 46#define ILOC3_P 0x06 /* Lock Way 3 */ 47#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */ 48 49/* ** Masks */ 50#define ENIM 0x00000001 /* Enable L1 Code Memory */ 51#define ENICPLB 0x00000002 /* Enable ICPLB */ 52#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */ 53#define ILOC0 0x00000008 /* Lock Way 0 */ 54#define ILOC1 0x00000010 /* Lock Way 1 */ 55#define ILOC2 0x00000020 /* Lock Way 2 */ 56#define ILOC3 0x00000040 /* Lock Way 3 */ 57#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */ 58 59/* DCPLB_DATA and ICPLB_DATA Registers */ 60/* ** Bit Positions */ 61#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ 62#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ 63#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ 64 65/* ** Masks */ 66#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ 67#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ 68#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ 69#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ 70#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ 71#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ 72#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ 73#define PAGE_SIZE_MASK 0x00030000 /* the bits for the page_size field */ 74#define PAGE_SIZE_SHIFT 16 75#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */ 76#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ 77#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ 78 79/* ICPLB_DATA only */ 80#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ 81 82/* DCPLB_DATA only */ 83#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ 84#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ 85#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ 86#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ 87 /* 1= allocate cache lines on write-through writes. */ 88#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ 89 90/* ITEST_COMMAND and DTEST_COMMAND Registers */ 91/* ** Masks */ 92#define TEST_READ 0x00000000 /* Read Access */ 93#define TEST_WRITE 0x00000002 /* Write Access */ 94#define TEST_TAG 0x00000000 /* Access TAG */ 95#define TEST_DATA 0x00000004 /* Access DATA */ 96#define TEST_DW0 0x00000000 /* Select Double Word 0 */ 97#define TEST_DW1 0x00000008 /* Select Double Word 1 */ 98#define TEST_DW2 0x00000010 /* Select Double Word 2 */ 99#define TEST_DW3 0x00000018 /* Select Double Word 3 */ 100#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ 101#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ 102#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ 103#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ 104#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */ 105#define TEST_WAY0 0x00000000 /* Access Way0 */ 106#define TEST_WAY1 0x04000000 /* Access Way1 */ 107 108/* ** ITEST_COMMAND only */ 109#define TEST_WAY2 0x08000000 /* Access Way2 */ 110#define TEST_WAY3 0x0C000000 /* Access Way3 */ 111 112/* ** DTEST_COMMAND only */ 113#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ 114#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ 115 116#endif 117