uboot/include/configs/MVBC_P.h
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   1/*
   2 * (C) Copyright 2003-2004
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2004-2008
   6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#ifndef __CONFIG_H
  28#define __CONFIG_H
  29
  30#include <version.h>
  31
  32#define CONFIG_MPC5xxx  1
  33#define CONFIG_MPC5200  1
  34
  35#define CONFIG_SYS_MPC5XXX_CLKIN        33000000
  36
  37#define BOOTFLAG_COLD           0x01
  38#define BOOTFLAG_WARM           0x02
  39
  40#define CONFIG_MISC_INIT_R      1
  41
  42#define CONFIG_SYS_CACHELINE_SIZE       32
  43#ifdef CONFIG_CMD_KGDB
  44#define CONFIG_SYS_CACHELINE_SHIFT      5
  45#endif
  46
  47#define CONFIG_PSC_CONSOLE      1
  48#define CONFIG_BAUDRATE         115200
  49#define CONFIG_SYS_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200, 230400}
  50
  51#define CONFIG_PCI              1
  52#define CONFIG_PCI_PNP          1
  53#undef  CONFIG_PCI_SCAN_SHOW
  54#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  55
  56#define CONFIG_PCI_MEM_BUS      0x40000000
  57#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  58#define CONFIG_PCI_MEM_SIZE     0x10000000
  59
  60#define CONFIG_PCI_IO_BUS       0x50000000
  61#define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  62#define CONFIG_PCI_IO_SIZE      0x01000000
  63
  64#define CONFIG_SYS_XLB_PIPELINING       1
  65#define CONFIG_HIGH_BATS        1
  66
  67#define MV_CI                   mvBlueCOUGAR-P
  68#define MV_VCI                  mvBlueCOUGAR-P
  69#define MV_FPGA_DATA            0xff860000
  70#define MV_FPGA_SIZE            0
  71#define MV_KERNEL_ADDR          0xffd00000
  72#define MV_INITRD_ADDR          0xff900000
  73#define MV_INITRD_LENGTH        0x00400000
  74#define MV_SCRATCH_ADDR         0x00000000
  75#define MV_SCRATCH_LENGTH       MV_INITRD_LENGTH
  76#define MV_SCRIPT_ADDR          0xff840000
  77#define MV_SCRIPT_ADDR2         0xff850000
  78#define MV_DTB_ADDR             0xfffc0000
  79
  80#define CONFIG_SHOW_BOOT_PROGRESS 1
  81
  82#define MV_KERNEL_ADDR_RAM      0x00100000
  83#define MV_DTB_ADDR_RAM         0x00600000
  84#define MV_INITRD_ADDR_RAM      0x01000000
  85
  86/* pass open firmware flat tree */
  87#define CONFIG_OF_LIBFDT        1
  88#define CONFIG_OF_BOARD_SETUP   1
  89
  90#define OF_CPU                  "PowerPC,5200@0"
  91#define OF_SOC                  "soc5200@f0000000"
  92#define OF_TBCLK                (bd->bi_busfreq / 4)
  93#define MV_DTB_NAME             mvbc-p.dtb
  94#define CONFIG_OF_STDOUT_VIA_ALIAS      1
  95
  96/*
  97 * Supported commands
  98 */
  99#include <config_cmd_default.h>
 100
 101#define CONFIG_CMD_CACHE
 102#define CONFIG_CMD_NET
 103#define CONFIG_CMD_PING
 104#define CONFIG_CMD_DHCP
 105#define CONFIG_CMD_SDRAM
 106#define CONFIG_CMD_PCI
 107#define CONFIG_CMD_FPGA
 108#define CONFIG_CMD_I2C
 109
 110#undef CONFIG_WATCHDOG
 111
 112#define CONFIG_BOOTP_VENDOREX
 113#define CONFIG_BOOTP_SUBNETMASK
 114#define CONFIG_BOOTP_GATEWAY
 115#define CONFIG_BOOTP_DNS
 116#define CONFIG_BOOTP_DNS2
 117#define CONFIG_BOOTP_HOSTNAME
 118#define CONFIG_BOOTP_BOOTFILESIZE
 119#define CONFIG_BOOTP_BOOTPATH
 120#define CONFIG_BOOTP_NTPSERVER
 121#define CONFIG_BOOTP_RANDOM_DELAY
 122#define CONFIG_BOOTP_SEND_HOSTNAME
 123
 124/*
 125 * Autoboot
 126 */
 127#define CONFIG_BOOTDELAY                2
 128#define CONFIG_AUTOBOOT_KEYED
 129#define CONFIG_AUTOBOOT_STOP_STR        "s"
 130#define CONFIG_ZERO_BOOTDELAY_CHECK
 131#define CONFIG_RESET_TO_RETRY           1000
 132
 133#define CONFIG_BOOTCOMMAND      "if imi ${script_addr}; \
 134                                        then source ${script_addr};     \
 135                                        else source ${script_addr2};    \
 136                                fi;"
 137
 138#define CONFIG_BOOTARGS         "root=/dev/ram ro rootfstype=squashfs"
 139#define CONFIG_ENV_OVERWRITE
 140
 141#define XMK_STR(x)      #x
 142#define MK_STR(x)       XMK_STR(x)
 143
 144#define CONFIG_EXTRA_ENV_SETTINGS                               \
 145        "console_nr=0\0"                                        \
 146        "console=yes\0"                                         \
 147        "stdin=serial\0"                                        \
 148        "stdout=serial\0"                                       \
 149        "stderr=serial\0"                                       \
 150        "fpga=0\0"                                              \
 151        "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"                   \
 152        "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"               \
 153        "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0"              \
 154        "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0"            \
 155        "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0"           \
 156        "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"   \
 157        "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0"           \
 158        "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"   \
 159        "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0"       \
 160        "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0"                 \
 161        "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"         \
 162        "dtb_name=" MK_STR(MV_DTB_NAME) "\0"                    \
 163        "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0"         \
 164        "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0"     \
 165        "mv_version=" U_BOOT_VERSION "\0"                       \
 166        "dhcp_client_id=" MK_STR(MV_CI) "\0"                    \
 167        "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"     \
 168        "netretry=no\0"                                         \
 169        "use_static_ipaddr=no\0"                                \
 170        "static_ipaddr=192.168.90.10\0"                         \
 171        "static_netmask=255.255.255.0\0"                        \
 172        "static_gateway=0.0.0.0\0"                              \
 173        "initrd_name=uInitrd.mvbc-p-rfs\0"                      \
 174        "zcip=no\0"                                             \
 175        "netboot=yes\0"                                         \
 176        "mvtest=Ff\0"                                           \
 177        "tried_bootfromflash=no\0"                              \
 178        "tried_bootfromnet=no\0"                                \
 179        "use_dhcp=yes\0"                                        \
 180        "gev_start=yes\0"                                       \
 181        "mvbcdma_debug=0\0"                                     \
 182        "mvbcia_debug=0\0"                                      \
 183        "propdev_debug=0\0"                                     \
 184        "gevss_debug=0\0"                                       \
 185        "watchdog=1\0"                                          \
 186        "sensor_cnt=1\0"                                        \
 187        ""
 188
 189#undef XMK_STR
 190#undef MK_STR
 191
 192/*
 193 * IPB Bus clocking configuration.
 194 */
 195#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
 196#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 197
 198/*
 199 * Flash configuration
 200 */
 201#undef  CONFIG_FLASH_16BIT
 202#define CONFIG_SYS_FLASH_CFI
 203#define CONFIG_FLASH_CFI_DRIVER
 204#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
 205#define CONFIG_SYS_FLASH_EMPTY_INFO
 206
 207#define CONFIG_SYS_FLASH_ERASE_TOUT     50000
 208#define CONFIG_SYS_FLASH_WRITE_TOUT     1000
 209
 210#define CONFIG_SYS_MAX_FLASH_BANKS      1
 211#define CONFIG_SYS_MAX_FLASH_SECT       256
 212
 213#define CONFIG_SYS_LOWBOOT
 214#define CONFIG_SYS_FLASH_BASE           TEXT_BASE
 215#define CONFIG_SYS_FLASH_SIZE           0x00800000
 216
 217/*
 218 * Environment settings
 219 */
 220#define CONFIG_ENV_IS_IN_FLASH
 221#undef  CONFIG_SYS_FLASH_PROTECTION
 222
 223#define CONFIG_ENV_ADDR         0xFFFE0000
 224#define CONFIG_ENV_SIZE         0x10000
 225#define CONFIG_ENV_SECT_SIZE    0x10000
 226#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
 227#define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 228
 229/*
 230 * Memory map
 231 */
 232#define CONFIG_SYS_MBAR         0xF0000000
 233#define CONFIG_SYS_SDRAM_BASE           0x00000000
 234#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 235
 236#define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 237#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
 238
 239#define CONFIG_SYS_GBL_DATA_SIZE        128
 240#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 241#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 242
 243#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 244#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 245#define CONFIG_SYS_RAMBOOT              1
 246#endif
 247
 248/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 249#define CONFIG_SYS_MONITOR_LEN          (512 << 10)
 250#define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 251#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 252
 253/*
 254 * I2C configuration
 255 */
 256#define CONFIG_HARD_I2C         1
 257#define CONFIG_SYS_I2C_MODULE   1
 258#define CONFIG_SYS_I2C_SPEED    86000
 259#define CONFIG_SYS_I2C_SLAVE    0x7F
 260
 261/*
 262 * Ethernet configuration
 263 */
 264#define CONFIG_NET_MULTI
 265#define CONFIG_NET_RETRY_COUNT 5
 266
 267#define CONFIG_E1000
 268#define CONFIG_E1000_FALLBACK_MAC       { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
 269#undef CONFIG_MPC5xxx_FEC
 270#undef CONFIG_PHY_ADDR
 271#define CONFIG_NETDEV           eth0
 272
 273/*
 274 * Miscellaneous configurable options
 275 */
 276#define CONFIG_SYS_HUSH_PARSER
 277#define CONFIG_CMDLINE_EDITING
 278#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 279#undef  CONFIG_SYS_LONGHELP
 280#define CONFIG_SYS_PROMPT               "=> "
 281#ifdef CONFIG_CMD_KGDB
 282#define CONFIG_SYS_CBSIZE               1024
 283#else
 284#define CONFIG_SYS_CBSIZE               256
 285#endif
 286#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 287#define CONFIG_SYS_MAXARGS              16
 288#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 289
 290#define CONFIG_SYS_MEMTEST_START        0x00800000
 291#define CONFIG_SYS_MEMTEST_END          0x02f00000
 292
 293#define CONFIG_SYS_HZ                   1000
 294
 295/* default load address */
 296#define CONFIG_SYS_LOAD_ADDR            0x02000000
 297/* default location for tftp and bootm */
 298#define CONFIG_LOADADDR         0x00200000
 299
 300/*
 301 * Various low-level settings
 302 */
 303#define CONFIG_SYS_GPS_PORT_CONFIG      0x20000004
 304
 305#define CONFIG_SYS_HID0_INIT            (HID0_ICE | HID0_ICFI)
 306#define CONFIG_SYS_HID0_FINAL           HID0_ICE
 307
 308#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 309#define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 310#define CONFIG_SYS_BOOTCS_CFG           0x00047800
 311#define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 312#define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 313
 314#define CONFIG_SYS_CS_BURST             0x000000f0
 315#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
 316
 317#define CONFIG_SYS_RESET_ADDRESS        0x00000100
 318
 319#undef FPGA_DEBUG
 320#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
 321#define CONFIG_FPGA             CONFIG_SYS_ALTERA_CYCLON2
 322#define CONFIG_FPGA_ALTERA      1
 323#define CONFIG_FPGA_CYCLON2     1
 324#define CONFIG_FPGA_COUNT       1
 325
 326#endif
 327