1/* 2 * (C) Copyright 2000 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 37#define CONFIG_MVS 1 /* ...on a MVsensor module */ 38#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */ 39#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */ 40 41#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 42 43#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */ 44#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ 45#undef CONFIG_8xx_CONS_NONE 46#define CONFIG_BAUDRATE 115200 /* console baudrate */ 47#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */ 48 49#define CONFIG_PREBOOT "echo;" \ 50 "echo To mount root over NFS use \"run bootnet\";" \ 51 "echo To mount root from FLASH use \"run bootflash\";" \ 52 "echo" 53#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" 54#define CONFIG_BOOTCOMMAND \ 55 "bootp; " \ 56 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 58 "bootm" 59 60#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 61#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 62 63#define CONFIG_WATCHDOG /* watchdog disabled/enabled */ 64 65#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */ 66 67#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 68 69 70/* 71 * BOOTP options 72 */ 73#define CONFIG_BOOTP_SUBNETMASK 74#define CONFIG_BOOTP_GATEWAY 75#define CONFIG_BOOTP_HOSTNAME 76#define CONFIG_BOOTP_BOOTPATH 77#define CONFIG_BOOTP_VENDOREX 78 79#undef CONFIG_MAC_PARTITION 80#undef CONFIG_DOS_PARTITION 81 82#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 83 84 85/* 86 * Command line configuration. 87 */ 88#define CONFIG_CMD_LOADS 89#define CONFIG_CMD_LOADB 90#define CONFIG_CMD_IMI 91#define CONFIG_CMD_FLASH 92#define CONFIG_CMD_MEMORY 93#define CONFIG_CMD_NET 94#define CONFIG_CMD_DHCP 95#define CONFIG_CMD_SAVEENV 96#define CONFIG_CMD_BOOTD 97#define CONFIG_CMD_RUN 98 99 100/* 101 * Miscellaneous configurable options 102 */ 103#undef CONFIG_SYS_LONGHELP /* undef to save memory */ 104#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 105 106#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */ 107#ifdef CONFIG_SYS_HUSH_PARSER 108#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 109#endif 110 111#if defined(CONFIG_CMD_KGDB) 112#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 113#else 114#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 115#endif 116#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 118#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 119 120#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 121#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 122 123#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 124 125#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 126 127#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 128 129/* 130 * Low Level Configuration Settings 131 * (address mappings, register initial values, etc.) 132 * You should know what you are doing if you make changes here. 133 */ 134/*----------------------------------------------------------------------- 135 * Internal Memory Mapped Register 136 */ 137#define CONFIG_SYS_IMMR 0xFFF00000 138 139/*----------------------------------------------------------------------- 140 * Definitions for initial stack pointer and data area (in DPRAM) 141 */ 142#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 143#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 144#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 145#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 146#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 147 148/*----------------------------------------------------------------------- 149 * Start addresses for the final memory configuration 150 * (Set up by the startup code) 151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 152 */ 153#define CONFIG_SYS_SDRAM_BASE 0x00000000 154#define CONFIG_SYS_FLASH_BASE 0x40000000 155 156#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */ 157 158#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 159#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 160 161/* 162 * For booting Linux, the board info and command line data 163 * have to be in the first 8 MB of memory, since this is 164 * the maximum mapped by the Linux kernel during initialization. 165 */ 166#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 167 168/*----------------------------------------------------------------------- 169 * FLASH organization 170 */ 171#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 172#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */ 173 174#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 175#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 176 177#define CONFIG_ENV_IS_IN_FLASH 1 178 179/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */ 180#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */ 181#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */ 182 183/*----------------------------------------------------------------------- 184 * Cache Configuration 185 */ 186#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 187#if defined(CONFIG_CMD_KGDB) 188#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 189#endif 190 191/*----------------------------------------------------------------------- 192 * SYPCR - System Protection Control 11-9 193 * SYPCR can only be written once after reset! 194 *----------------------------------------------------------------------- 195 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 196 */ 197#if defined(CONFIG_WATCHDOG) 198#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 199 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 200#else 201#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 202#endif 203 204/*----------------------------------------------------------------------- 205 * SIUMCR - SIU Module Configuration 11-6 206 *----------------------------------------------------------------------- 207 * PCMCIA config., multi-function pin tri-state 208 */ 209#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 210 211/*----------------------------------------------------------------------- 212 * TBSCR - Time Base Status and Control 11-26 213 *----------------------------------------------------------------------- 214 * Clear Reference Interrupt Status, Timebase freezing enabled 215 */ 216#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 217 218/*----------------------------------------------------------------------- 219 * RTCSC - Real-Time Clock Status and Control Register 11-27 220 *----------------------------------------------------------------------- 221 */ 222#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 223 224/*----------------------------------------------------------------------- 225 * PISCR - Periodic Interrupt Status and Control 11-31 226 *----------------------------------------------------------------------- 227 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 228 */ 229#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 230 231/*----------------------------------------------------------------------- 232 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 233 *----------------------------------------------------------------------- 234 * Reset PLL lock status sticky bit, timer expired status bit and timer 235 * interrupt status bit 236 * 237 */ 238#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 239 240/*----------------------------------------------------------------------- 241 * SCCR - System Clock and reset Control Register 15-27 242 *----------------------------------------------------------------------- 243 * Set clock output, timebase and RTC source and divider, 244 * power management and some other internal clocks 245 */ 246#define SCCR_MASK SCCR_EBDF11 247#define CONFIG_SYS_SCCR (SCCR_TBS | \ 248 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 249 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 250 SCCR_DFALCD00) 251 252/*----------------------------------------------------------------------- 253 * PCMCIA stuff 254 *----------------------------------------------------------------------- 255 * 256 */ 257#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 258#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 259#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 260#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 261#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 262#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 263#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 264#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 265 266/*----------------------------------------------------------------------- 267 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 268 *----------------------------------------------------------------------- 269 */ 270 271#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */ 272 273#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ 274#undef CONFIG_IDE_LED /* LED for ide not supported */ 275#undef CONFIG_IDE_RESET /* reset for ide not supported */ 276 277#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */ 278#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */ 279 280 281#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 282 283#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 284 285/* Offset for data I/O */ 286#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 287 288/* Offset for normal register accesses */ 289#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 290 291/* Offset for alternate registers */ 292#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 293 294/*----------------------------------------------------------------------- 295 * 296 *----------------------------------------------------------------------- 297 * 298 */ 299/*#define CONFIG_SYS_DER 0x2002000F*/ 300#define CONFIG_SYS_DER 0 301 302/* 303 * Init Memory Controller: 304 * 305 * BR0/1 and OR0/1 (FLASH) 306 */ 307 308#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 309#undef FLASH_BASE1_PRELIM 310 311/* used to re-map FLASH both when starting from SRAM or FLASH: 312 * restrict access enough to keep SRAM working (if any) 313 * but not too much to meddle with FLASH accesses 314 */ 315#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 316#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 317 318 319/* 320 * FLASH timing: 321 */ 322/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ 323#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 324 OR_SCY_2_CLK | OR_EHTR | OR_BI) 325/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 326/* 327#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ 328 OR_SCY_5_CLK | OR_EHTR) 329*/ 330 331#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 332#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 333#ifdef CONFIG_MVS_16BIT_FLASH 334#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) 335#else 336#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) 337#endif 338 339#undef CONFIG_SYS_OR1_REMAP 340#undef CONFIG_SYS_OR1_PRELIM 341#undef CONFIG_SYS_BR1_PRELIM 342/* 343 * BR2/3 and OR2/3 (SDRAM) 344 * 345 */ 346#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 347#undef SDRAM_BASE3_PRELIM 348#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 349 350/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 351#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 352 353#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 354#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 355 356#undef CONFIG_SYS_OR3_PRELIM 357#undef CONFIG_SYS_BR3_PRELIM 358 359 360/* 361 * Memory Periodic Timer Prescaler 362 * 363 * The Divider for PTA (refresh timer) configuration is based on an 364 * example SDRAM configuration (64 MBit, one bank). The adjustment to 365 * the number of chip selects (NCS) and the actually needed refresh 366 * rate is done by setting MPTPR. 367 * 368 * PTA is calculated from 369 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 370 * 371 * gclk CPU clock (not bus clock!) 372 * Trefresh Refresh cycle * 4 (four word bursts used) 373 * 374 * 4096 Rows from SDRAM example configuration 375 * 1000 factor s -> ms 376 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 377 * 4 Number of refresh cycles per period 378 * 64 Refresh cycle in ms per number of rows 379 * -------------------------------------------- 380 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 381 * 382 * 50 MHz => 50.000.000 / Divider = 98 383 * 66 Mhz => 66.000.000 / Divider = 129 384 * 80 Mhz => 80.000.000 / Divider = 156 385 */ 386#define CONFIG_SYS_MAMR_PTA 98 387 388/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 389#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 390#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 391 392/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 393#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 394#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 395 396/* 397 * MAMR settings for SDRAM 398 */ 399 400/* 8 column SDRAM */ 401#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 402 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 403 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 404/* 9 column SDRAM */ 405#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 406 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \ 407 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 408 409 410/* 411 * Internal Definitions 412 * 413 * Boot Flags 414 */ 415#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 416#define BOOTFLAG_WARM 0x02 /* Software reboot */ 417 418#endif /* __CONFIG_H */ 419