LXR uboot/include/configs/VOM405.h

   1/*
   2 * (C) Copyright 2001-2004
   3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * board/config.h - configuration options, board specific
  26 */
  27#ifndef __CONFIG_H
  28#define __CONFIG_H
  29
  30/*
  31 * High Level Configuration Options
  32 * (easy to change)
  33 */
  34#define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  35#define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  36#define CONFIG_VOM405           1       /* ...on a VOM405 board         */
  37
  38#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  39#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  40
  41#define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  42
  43#define CONFIG_BAUDRATE         9600
  44#define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  45
  46#undef  CONFIG_BOOTARGS
  47#undef  CONFIG_BOOTCOMMAND
  48
  49#define CONFIG_PREBOOT                  /* enable preboot variable      */
  50
  51#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  52
  53#define CONFIG_NET_MULTI        1
  54#undef  CONFIG_HAS_ETH1
  55
  56#define CONFIG_PPC4xx_EMAC
  57#define CONFIG_MII              1       /* MII PHY management           */
  58#define CONFIG_PHY_ADDR         0       /* PHY address                  */
  59#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  60#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  61
  62/*
  63 * BOOTP options
  64 */
  65#define CONFIG_BOOTP_SUBNETMASK
  66#define CONFIG_BOOTP_GATEWAY
  67#define CONFIG_BOOTP_HOSTNAME
  68#define CONFIG_BOOTP_BOOTPATH
  69#define CONFIG_BOOTP_DNS
  70#define CONFIG_BOOTP_DNS2
  71#define CONFIG_BOOTP_SEND_HOSTNAME
  72
  73/*
  74 * Command line configuration.
  75 */
  76#include <config_cmd_default.h>
  77
  78#define CONFIG_CMD_DHCP
  79#define CONFIG_CMD_BSP
  80#define CONFIG_CMD_IRQ
  81#define CONFIG_CMD_ELF
  82#define CONFIG_CMD_I2C
  83#define CONFIG_CMD_MII
  84#define CONFIG_CMD_PING
  85#define CONFIG_CMD_EEPROM
  86
  87#define CONFIG_OF_LIBFDT
  88#define CONFIG_OF_BOARD_SETUP
  89
  90#undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  91
  92#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  93
  94#undef  CONFIG_PRAM                     /* no "protected RAM"           */
  95
  96/*
  97 * Miscellaneous configurable options
  98 */
  99#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 100#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 101
 102#undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 103#ifdef  CONFIG_SYS_HUSH_PARSER
 104#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 105#endif
 106
 107#if defined(CONFIG_CMD_KGDB)
 108#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 109#else
 110#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 111#endif
 112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 113#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 114#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 115
 116#define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 117
 118#define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 119
 120#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 121#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 122
 123#undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 124#define CONFIG_SYS_BASE_BAUD        691200
 125#undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 126
 127/* The following table includes the supported baudrates */
 128#define CONFIG_SYS_BAUDRATE_TABLE       \
 129        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 130         57600, 115200, 230400, 460800, 921600 }
 131
 132#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 133#define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 134
 135#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 136
 137#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 138#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 139
 140#define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 141
 142#define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 143
 144/*
 145 * For booting Linux, the board info and command line data
 146 * have to be in the first 8 MB of memory, since this is
 147 * the maximum mapped by the Linux kernel during initialization.
 148 */
 149#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 150/*
 151 * FLASH organization
 152 */
 153#define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 154
 155#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 156#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 157
 158#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 159#define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 160
 161#define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 162#define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 163#define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 164/*
 165 * The following defines are added for buggy IOP480 byte interface.
 166 * All other boards should use the standard values (CPCI405 etc.)
 167 */
 168#define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 169#define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 170#define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 171
 172#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 173
 174/*
 175 * Start addresses for the final memory configuration
 176 * (Set up by the startup code)
 177 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 178 */
 179#define CONFIG_SYS_SDRAM_BASE           0x00000000
 180#define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 181#define CONFIG_SYS_MONITOR_BASE         TEXT_BASE
 182#define CONFIG_SYS_MONITOR_LEN          (~(TEXT_BASE) + 1)
 183#define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 184
 185#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 186# define CONFIG_SYS_RAMBOOT             1
 187#else
 188# undef CONFIG_SYS_RAMBOOT
 189#endif
 190
 191/*
 192 * Environment Variable setup
 193 */
 194#define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 195#define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 196#define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 197                                   /* total size of a CAT24WC16 is 2048 bytes */
 198
 199#define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 200#define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 201
 202/*
 203 * I2C EEPROM (CAT24WC16) for environment
 204 */
 205#define CONFIG_HARD_I2C                 /* I2c with hardware support */
 206#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 207#define CONFIG_SYS_I2C_SLAVE            0x7F
 208
 209#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 210#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 211/* mask of address bits that overflow into the "EEPROM chip address"    */
 212#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 213#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 214                                        /* 16 byte page write mode using*/
 215                                        /* last 4 bits of the address   */
 216#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 217
 218/*
 219 * External Bus Controller (EBC) Setup
 220 */
 221#define CAN_BA          0xF0000000          /* CAN Base Address                 */
 222
 223/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 224#define CONFIG_SYS_EBC_PB0AP            0x92015480
 225#define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 226
 227/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 228#define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 229#define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 230
 231/*
 232 * FPGA stuff
 233 */
 234#define CONFIG_SYS_XSVF_DEFAULT_ADDR    0xfffc0000
 235
 236/* FPGA program pin configuration */
 237#define CONFIG_SYS_FPGA_PRG             0x04000000  /* JTAG TMS pin (ppc output)     */
 238#define CONFIG_SYS_FPGA_CLK             0x02000000  /* JTAG TCK pin (ppc output)     */
 239#define CONFIG_SYS_FPGA_DATA            0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 240#define CONFIG_SYS_FPGA_INIT            0x00010000  /* unused (ppc input)            */
 241#define CONFIG_SYS_FPGA_DONE            0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 242
 243/*
 244 * Definitions for initial stack pointer and data area (in data cache)
 245 */
 246/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 247#define CONFIG_SYS_TEMP_STACK_OCM         1
 248
 249/* On Chip Memory location */
 250#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 251#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 252#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 253#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
 254
 255#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 256#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 257#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 258
 259/*
 260 * Definitions for GPIO setup (PPC405EP specific)
 261 *
 262 * GPIO0[0]     - External Bus Controller BLAST output
 263 * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 264 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 265 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 266 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 267 * GPIO0[24-27] - UART0 control signal inputs/outputs
 268 * GPIO0[28-29] - UART1 data signal input/output
 269 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 270 */
 271/* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
 272/* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
 273/* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
 274/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 275#define CONFIG_SYS_GPIO0_OSRH           0x40000500  /*  0 ... 15 */
 276#define CONFIG_SYS_GPIO0_OSRL           0x00000110  /* 16 ... 31 */
 277#define CONFIG_SYS_GPIO0_ISR1H          0x00000000  /*  0 ... 15 */
 278#define CONFIG_SYS_GPIO0_ISR1L          0x14000045  /* 16 ... 31 */
 279#define CONFIG_SYS_GPIO0_TSRH           0x00000000  /*  0 ... 15 */
 280#define CONFIG_SYS_GPIO0_TSRL           0x00000000  /* 16 ... 31 */
 281#define CONFIG_SYS_GPIO0_TCR            0xF7FE0014  /*  0 ... 31 */
 282
 283/*
 284 * Internal Definitions
 285 *
 286 * Boot Flags
 287 */
 288#define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 289#define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 290
 291/*
 292 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 293 * This value will be set if iic boot eprom is disabled.
 294 */
 295#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 296#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 297
 298#endif  /* __CONFIG_H */
 299