LXR uboot/include/configs/inka4x0.h

   1/*
   2 * (C) Copyright 2009
   3 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   4 *
   5 * (C) Copyright 2003-2005
   6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#ifndef __CONFIG_H
  28#define __CONFIG_H
  29
  30/*
  31 * High Level Configuration Options
  32 * (easy to change)
  33 */
  34
  35#define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  36#define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU)      */
  37#define CONFIG_INKA4X0          1       /* INKA4x0 board                        */
  38
  39#define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  40
  41#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
  42#define BOOTFLAG_WARM           0x02    /* Software reboot                      */
  43
  44#define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  45
  46#define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  47
  48/*
  49 * Serial console configuration
  50 */
  51#define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  52#define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  53#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  54
  55/*
  56 * PCI Mapping:
  57 * 0x40000000 - 0x4fffffff - PCI Memory
  58 * 0x50000000 - 0x50ffffff - PCI IO Space
  59 */
  60#define CONFIG_PCI              1
  61#define CONFIG_PCI_PNP          1
  62#define CONFIG_PCI_SCAN_SHOW    1
  63#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  64
  65#define CONFIG_PCI_MEM_BUS      0x40000000
  66#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  67#define CONFIG_PCI_MEM_SIZE     0x10000000
  68
  69#define CONFIG_PCI_IO_BUS       0x50000000
  70#define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  71#define CONFIG_PCI_IO_SIZE      0x01000000
  72
  73#define CONFIG_SYS_XLB_PIPELINING       1
  74
  75/* Partitions */
  76#define CONFIG_MAC_PARTITION
  77#define CONFIG_DOS_PARTITION
  78#define CONFIG_ISO_PARTITION
  79
  80
  81/*
  82 * BOOTP options
  83 */
  84#define CONFIG_BOOTP_BOOTFILESIZE
  85#define CONFIG_BOOTP_BOOTPATH
  86#define CONFIG_BOOTP_GATEWAY
  87#define CONFIG_BOOTP_HOSTNAME
  88
  89
  90/*
  91 * Command line configuration.
  92 */
  93#include <config_cmd_default.h>
  94
  95#define CONFIG_CMD_DATE
  96#define CONFIG_CMD_DHCP
  97#define CONFIG_CMD_EXT2
  98#define CONFIG_CMD_FAT
  99#define CONFIG_CMD_IDE
 100#define CONFIG_CMD_NFS
 101#define CONFIG_CMD_PCI
 102#define CONFIG_CMD_PING
 103#define CONFIG_CMD_SNTP
 104#define CONFIG_CMD_USB
 105
 106#define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
 107
 108#if (TEXT_BASE == 0xFFE00000)           /* Boot low */
 109#   define CONFIG_SYS_LOWBOOT           1
 110#endif
 111
 112/*
 113 * Autobooting
 114 */
 115#define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 116
 117#define CONFIG_PREBOOT  "echo;" \
 118        "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 119        "echo"
 120
 121#undef  CONFIG_BOOTARGS
 122
 123#define CONFIG_ETHADDR          00:a0:a4:03:00:00
 124#define CONFIG_OVERWRITE_ETHADDR_ONCE
 125
 126#define CONFIG_IPADDR           192.168.100.2
 127#define CONFIG_SERVERIP         192.168.100.1
 128#define CONFIG_NETMASK          255.255.255.0
 129#define HOSTNAME                inka4x0
 130#define CONFIG_BOOTFILE         /tftpboot/inka4x0/uImage
 131#define CONFIG_ROOTPATH         /opt/eldk/ppc_6xx
 132
 133#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 134        "netdev=eth0\0"                                                 \
 135        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 136                "nfsroot=${serverip}:${rootpath}\0"                     \
 137        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 138        "addip=setenv bootargs ${bootargs} "                            \
 139                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 140                ":${hostname}:${netdev}:off panic=1\0"                  \
 141        "addcons=setenv bootargs ${bootargs} "                          \
 142                "console=ttyS0,${baudrate}\0"                           \
 143        "flash_nfs=run nfsargs addip addcons;"                          \
 144                "bootm ${kernel_addr}\0"                                \
 145        "net_nfs=tftp 200000 ${bootfile};"                              \
 146                "run nfsargs addip addcons;bootm\0"                     \
 147        "enable_disp=mw.l 100000 04000000 1;"                           \
 148                "cp.l 100000 f0000b20 1;"                               \
 149                "cp.l 100000 f0000b28 1\0"                              \
 150        "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 151        "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 152                "run ideargs addip addcons enable_disp;bootm\0"         \
 153        "brightness=255\0"                                              \
 154        ""
 155
 156#define CONFIG_BOOTCOMMAND      "run ide_boot"
 157
 158/*
 159 * IPB Bus clocking configuration.
 160 */
 161#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 162
 163/*
 164 * Flash configuration
 165 */
 166#define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 167#define CONFIG_FLASH_CFI_DRIVER 1
 168#define CONFIG_SYS_FLASH_BASE           0xffe00000
 169#define CONFIG_SYS_FLASH_SIZE           0x00200000
 170#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 171#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 172#define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 173#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 174
 175/*
 176 * Environment settings
 177 */
 178#define CONFIG_ENV_IS_IN_FLASH  1
 179#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x4000)
 180#define CONFIG_ENV_SIZE         0x2000
 181#define CONFIG_ENV_SECT_SIZE    0x2000
 182#define CONFIG_ENV_OVERWRITE    1
 183#define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 184
 185/*
 186 * Memory map
 187 */
 188#define CONFIG_SYS_MBAR         0xF0000000
 189#define CONFIG_SYS_SDRAM_BASE           0x00000000
 190#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 191
 192/*
 193 * SDRAM controller configuration
 194 */
 195#undef CONFIG_SDR_MT48LC16M16A2
 196#undef CONFIG_DDR_MT46V16M16
 197#undef CONFIG_DDR_MT46V32M16
 198#undef CONFIG_DDR_HYB25D512160BF
 199#define CONFIG_DDR_K4H511638C
 200
 201/* Use ON-Chip SRAM until RAM will be available */
 202#define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 203#ifdef CONFIG_POST
 204/* preserve space for the post_word at end of on-chip SRAM */
 205#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
 206#else
 207#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
 208#endif
 209
 210
 211#define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 212#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 213#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 214
 215#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 216#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 217#   define CONFIG_SYS_RAMBOOT           1
 218#endif
 219
 220#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 221#define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 222#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 223
 224/*
 225 * Ethernet configuration
 226 */
 227#define CONFIG_MPC5xxx_FEC      1
 228#define CONFIG_MPC5xxx_FEC_MII100
 229/*
 230 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 231 */
 232/* #define CONFIG_MPC5xxx_FEC_MII10 */
 233#define CONFIG_PHY_ADDR         0x00
 234#define CONFIG_MII
 235
 236/*
 237 * GPIO configuration
 238 *
 239 * use CS1 as gpio_wkup_6 output
 240 *      Bit 0 (mask: 0x80000000): 0
 241 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 242 *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 243 *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 244 *            EEPROM
 245 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 246 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 247 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 248 * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 249 */
 250#define CONFIG_SYS_GPS_PORT_CONFIG      0x01501444
 251
 252/*
 253 * RTC configuration
 254 */
 255#define CONFIG_RTC_RTC4543      1       /* use external RTC */
 256
 257/*
 258 * Software (bit-bang) three wire serial configuration
 259 *
 260 * Note that we need the ifdefs because otherwise compilation of
 261 * mkimage.c fails.
 262 */
 263#define CONFIG_SOFT_TWS         1
 264
 265#ifdef TWS_IMPLEMENTATION
 266#include <mpc5xxx.h>
 267#include <asm/io.h>
 268
 269#define TWS_CE          MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
 270#define TWS_WR          MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
 271#define TWS_DATA        MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
 272#define TWS_CLK         MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
 273
 274static inline void tws_ce(unsigned bit)
 275{
 276        struct mpc5xxx_wu_gpio *wu_gpio =
 277                (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 278        if (bit)
 279                setbits_8(&wu_gpio->dvo, TWS_CE);
 280        else
 281                clrbits_8(&wu_gpio->dvo, TWS_CE);
 282}
 283
 284static inline void tws_wr(unsigned bit)
 285{
 286        struct mpc5xxx_wu_gpio *wu_gpio =
 287                (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 288        if (bit)
 289                setbits_8(&wu_gpio->dvo, TWS_WR);
 290        else
 291                clrbits_8(&wu_gpio->dvo, TWS_WR);
 292}
 293
 294static inline void tws_clk(unsigned bit)
 295{
 296        struct mpc5xxx_gpio *gpio =
 297                (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 298        if (bit)
 299                setbits_8(&gpio->sint_dvo, TWS_CLK);
 300        else
 301                clrbits_8(&gpio->sint_dvo, TWS_CLK);
 302}
 303
 304static inline void tws_data(unsigned bit)
 305{
 306        struct mpc5xxx_gpio *gpio =
 307                (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 308        if (bit)
 309                setbits_8(&gpio->sint_dvo, TWS_DATA);
 310        else
 311                clrbits_8(&gpio->sint_dvo, TWS_DATA);
 312}
 313
 314static inline unsigned tws_data_read(void)
 315{
 316        struct mpc5xxx_gpio *gpio =
 317                        (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 318        return !!(in_8(&gpio->sint_ival) & TWS_DATA);
 319}
 320
 321static inline void tws_data_config_output(unsigned output)
 322{
 323        struct mpc5xxx_gpio *gpio =
 324                (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 325        if (output)
 326                setbits_8(&gpio->sint_ddr, TWS_DATA);
 327        else
 328                clrbits_8(&gpio->sint_ddr, TWS_DATA);
 329}
 330#endif /* TWS_IMPLEMENTATION */
 331
 332/*
 333 * Miscellaneous configurable options
 334 */
 335#define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 336#define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 337#if defined(CONFIG_CMD_KGDB)
 338#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 339#else
 340#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 341#endif
 342#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 343#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 344#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 345
 346#define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 347#if defined(CONFIG_CMD_KGDB)
 348#  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 349#endif
 350
 351/* Enable an alternate, more extensive memory test */
 352#define CONFIG_SYS_ALT_MEMTEST
 353
 354#define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 355#define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 356
 357#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 358
 359#define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 360
 361/*
 362 * Enable loopw command.
 363 */
 364#define CONFIG_LOOPW
 365
 366/*
 367 * Various low-level settings
 368 */
 369#if defined(CONFIG_MPC5200)
 370#define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 371#define CONFIG_SYS_HID0_FINAL           HID0_ICE
 372#else
 373#define CONFIG_SYS_HID0_INIT            0
 374#define CONFIG_SYS_HID0_FINAL           0
 375#endif
 376
 377#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 378#define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 379#define CONFIG_SYS_BOOTCS_CFG           0x00087800 /* for pci_clk  = 66 MHz */
 380#define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 381#define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 382
 383/* 32Mbit SRAM @0x30000000 */
 384#define CONFIG_SYS_CS1_START            0x30000000
 385#define CONFIG_SYS_CS1_SIZE             0x00400000
 386#define CONFIG_SYS_CS1_CFG              0x31800 /* for pci_clk = 33 MHz */
 387
 388/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 389#define CONFIG_SYS_CS2_START            0x80000000
 390#define CONFIG_SYS_CS2_SIZE             0x0001000
 391#define CONFIG_SYS_CS2_CFG              0x21800  /* for pci_clk = 33 MHz */
 392
 393/* GPIO in @0x30400000 */
 394#define CONFIG_SYS_CS3_START            0x30400000
 395#define CONFIG_SYS_CS3_SIZE             0x00100000
 396#define CONFIG_SYS_CS3_CFG              0x31800 /* for pci_clk = 33 MHz */
 397
 398#define CONFIG_SYS_CS_BURST             0x00000000
 399#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 400
 401/*-----------------------------------------------------------------------
 402 * USB stuff
 403 *-----------------------------------------------------------------------
 404 */
 405#define CONFIG_USB_OHCI
 406#define CONFIG_USB_CLOCK        0x00015555
 407#define CONFIG_USB_CONFIG       0x00001000
 408#define CONFIG_USB_STORAGE
 409
 410/*-----------------------------------------------------------------------
 411 * IDE/ATA stuff Supports IDE harddisk
 412 *-----------------------------------------------------------------------
 413 */
 414
 415#undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 416
 417#undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 418#undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 419
 420#define CONFIG_IDE_PREINIT
 421
 422#define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 423#define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 424
 425#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 426#define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 427#define CONFIG_SYS_ATA_DATA_OFFSET      0x0060  /* Offset for data I/O          */
 428#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 429#define CONFIG_SYS_ATA_ALT_OFFSET       0x005C  /* Offset for alternate registers */
 430#define CONFIG_SYS_ATA_STRIDE          4        /* Interval between registers   */
 431
 432#define CONFIG_ATAPI            1
 433
 434#define CONFIG_SYS_BRIGHTNESS          0xFF     /* LCD Default Brightness (255 = off) */
 435
 436#endif /* __CONFIG_H */
 437