1/* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27/* 28 * High Level Configuration Options 29 * (easy to change) 30 */ 31#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 32#define CONFIG_MPC5200 33#define CONFIG_O2DNT 1 /* ... on O2DNT board */ 34 35#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 36 37#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 38#define BOOTFLAG_WARM 0x02 /* Software reboot */ 39 40#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 41 42/* 43 * Serial console configuration 44 */ 45#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ 46#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 47#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 48 49/* 50 * PCI Mapping: 51 * 0x40000000 - 0x4fffffff - PCI Memory 52 * 0x50000000 - 0x50ffffff - PCI IO Space 53 */ 54#define CONFIG_PCI 1 55#define CONFIG_PCI_PNP 1 56/* #define CONFIG_PCI_SCAN_SHOW 1 */ 57#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 58 59#define CONFIG_PCI_MEM_BUS 0x40000000 60#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 61#define CONFIG_PCI_MEM_SIZE 0x10000000 62 63#define CONFIG_PCI_IO_BUS 0x50000000 64#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 65#define CONFIG_PCI_IO_SIZE 0x01000000 66 67#define CONFIG_SYS_XLB_PIPELINING 1 68 69#define CONFIG_NET_MULTI 1 70#define CONFIG_EEPRO100 71#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 72#define CONFIG_NS8382X 1 73 74/* Partitions */ 75#define CONFIG_MAC_PARTITION 76#define CONFIG_DOS_PARTITION 77#define CONFIG_ISO_PARTITION 78 79#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 80 81 82/* 83 * BOOTP options 84 */ 85#define CONFIG_BOOTP_BOOTFILESIZE 86#define CONFIG_BOOTP_BOOTPATH 87#define CONFIG_BOOTP_GATEWAY 88#define CONFIG_BOOTP_HOSTNAME 89 90 91/* 92 * Command line configuration. 93 */ 94#include <config_cmd_default.h> 95 96#define CONFIG_CMD_EEPROM 97#define CONFIG_CMD_FAT 98#define CONFIG_CMD_I2C 99#define CONFIG_CMD_NFS 100#define CONFIG_CMD_MII 101#define CONFIG_CMD_PING 102#define CONFIG_CMD_PCI 103 104 105#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ 106# define CONFIG_SYS_LOWBOOT 1 107#else 108# error "TEXT_BASE must be 0xFF000000" 109#endif 110 111/* 112 * Autobooting 113 */ 114#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 115 116#define CONFIG_PREBOOT "echo;" \ 117 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 118 "echo" 119 120#undef CONFIG_BOOTARGS 121 122#define CONFIG_EXTRA_ENV_SETTINGS \ 123 "netdev=eth0\0" \ 124 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 125 "nfsroot=${serverip}:${rootpath}\0" \ 126 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 127 "addip=setenv bootargs ${bootargs} " \ 128 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 129 ":${hostname}:${netdev}:off panic=1\0" \ 130 "flash_nfs=run nfsargs addip;" \ 131 "bootm ${kernel_addr}\0" \ 132 "flash_self=run ramargs addip;" \ 133 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 134 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 135 "rootpath=/opt/eldk/ppc_82xx\0" \ 136 "bootfile=/tftpboot/MPC5200/uImage\0" \ 137 "" 138 139#define CONFIG_BOOTCOMMAND "run flash_self" 140 141#if defined(CONFIG_MPC5200) 142/* 143 * IPB Bus clocking configuration. 144 */ 145#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 146 147#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) 148/* 149 * PCI Bus clocking configuration 150 * 151 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if 152 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 153 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. 154 */ 155#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ 156#endif 157#endif 158 159/* 160 * I2C configuration 161 */ 162#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 163#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ 164 165#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 166#define CONFIG_SYS_I2C_SLAVE 0x7F 167 168/* 169 * EEPROM configuration: 170 * 171 * O2DNT board is equiped with Ramtron FRAM device FM24CL16 172 * 16 Kib Ferroelectric Nonvolatile serial RAM memory 173 * organized as 2048 x 8 bits and addressable as eight I2C devices 174 * 0x50 ... 0x57 each 256 bytes in size 175 * 176 */ 177#define CONFIG_SYS_I2C_FRAM 178#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 179#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 180#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 181/* 182 * There is no write delay with FRAM, write operations are performed at bus 183 * speed. Thus, no status polling or write delay is needed. 184 */ 185/*#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70*/ 186 187 188/* 189 * Flash configuration 190 */ 191#define CONFIG_SYS_FLASH_BASE 0xFF000000 192#define CONFIG_SYS_FLASH_SIZE 0x01000000 193#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) 194 195#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 196#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 197 198#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 199#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 200#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ 201#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 202 203/* 204 * Environment settings 205 */ 206#define CONFIG_ENV_IS_IN_FLASH 1 207#define CONFIG_ENV_SIZE 0x20000 208#define CONFIG_ENV_SECT_SIZE 0x20000 209#define CONFIG_ENV_OVERWRITE 1 210 211/* 212 * Memory map 213 */ 214#define CONFIG_SYS_MBAR 0xF0000000 215#define CONFIG_SYS_SDRAM_BASE 0x00000000 216#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 217 218/* Use SRAM until RAM will be available */ 219#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 220#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ 221 222 223#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 224#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 225#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 226 227#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 228#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 229#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 230#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 231 232/* 233 * Ethernet configuration 234 */ 235#define CONFIG_MPC5xxx_FEC 1 236#define CONFIG_MPC5xxx_FEC_MII100 237/* 238 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb 239 */ 240/* #define CONFIG_MPC5xxx_FEC_MII10 */ 241#define CONFIG_PHY_ADDR 0x00 242 243/* 244 * GPIO configuration 245 */ 246/*#define CONFIG_SYS_GPS_PORT_CONFIG 0x10002004 */ 247#define CONFIG_SYS_GPS_PORT_CONFIG 0x00002006 /* no CAN */ 248 249/* 250 * Miscellaneous configurable options 251 */ 252#define CONFIG_SYS_LONGHELP /* undef to save memory */ 253#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 254 255#if defined(CONFIG_CMD_KGDB) 256#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 257#else 258#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 259#endif 260#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 261#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 262#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 263 264#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 265#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 266 267#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 268 269#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 270 271#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 272#if defined(CONFIG_CMD_KGDB) 273# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 274#endif 275 276/* 277 * Various low-level settings 278 */ 279#if defined(CONFIG_MPC5200) 280#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 281#define CONFIG_SYS_HID0_FINAL HID0_ICE 282#else 283#define CONFIG_SYS_HID0_INIT 0 284#define CONFIG_SYS_HID0_FINAL 0 285#endif 286 287#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 288#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 289 290#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 291/* 292 * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). 293 */ 294#define CONFIG_SYS_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */ 295#else 296#define CONFIG_SYS_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */ 297#endif 298 299#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 300#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 301 302#define CONFIG_SYS_CS_BURST 0x00000000 303#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 304 305#define CONFIG_SYS_RESET_ADDRESS 0xff000000 306 307#endif /* __CONFIG_H */ 308