1/* 2 * (C) Copyright 2007 3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>. 4 * 5 * From: 6 * (C) Copyright 2003 7 * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#undef USE_VGA_GRAPHICS 32 33/* Memory Map 34 * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB) 35 * 0x74000000 .... 0x740FFFFF -> CS#6 36 * 0x74100000 .... 0x741FFFFF -> CS#7 37 * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB 38 * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE 39 * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB) 40 * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB) 41 * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB) 42 * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB) 43 * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored) 44 * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB) 45 * 46 * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1) 47 * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF) 48 * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF) 49 * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF) 50 * 0xEED00000 .... 0xEED00003 -> PCI-Bus 51 * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers 52 * 0xEF40003F .... 0xEF5FFFFF -> reserved 53 * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB) 54 * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB) 55 * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices 56 * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB) 57 * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices 58 * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB) 59 */ 60 61#define CONFIG_SC3 1 62#define CONFIG_4xx 1 63#define CONFIG_405GP 1 64 65#define CONFIG_BOARD_EARLY_INIT_F 1 66#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ 67 68/* 69 * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range 70 * If undefined, IDE access uses a seperat emulation with higher access speed. 71 * Consider to inform your Linux IDE driver about the different addresses! 72 * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE! 73 */ 74#define IDE_USES_ISA_EMULATION 75 76/*----------------------------------------------------------------------- 77 * Serial Port 78 *----------------------------------------------------------------------*/ 79#define CONFIG_SERIAL_MULTI 80#undef CONFIG_SERIAL_SOFTWARE_FIFO 81/* 82 * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input 83 * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature 84 */ 85#if CONFIG_SERIAL_SOFTWARE_FIFO 86 #define CONFIG_POWER_DOWN 87#endif 88 89/* 90 * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz 91 */ 92#define CONFIG_SYS_CLK_FREQ 33333333 93 94/* 95 * define CONFIG_BAUDRATE to the baudrate value you want to use as default 96 */ 97#define CONFIG_BAUDRATE 115200 98#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 99 100#define CONFIG_PREBOOT "echo;" \ 101 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 102 "echo" 103 104#undef CONFIG_BOOTARGS 105 106#define CONFIG_EXTRA_ENV_SETTINGS \ 107 "netdev=eth0\0" \ 108 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 109 "nfsroot=${serverip}:${rootpath}\0" \ 110 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 111 "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \ 112 "rootfstype=jffs2\0" \ 113 "addip=setenv bootargs ${bootargs} " \ 114 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 115 ":${hostname}:${netdev}:off panic=1\0" \ 116 "addcons=setenv bootargs ${bootargs} " \ 117 "console=ttyS0,${baudrate}\0" \ 118 "flash_nfs=run nfsargs addip addcons;" \ 119 "bootm ${kernel_addr}\0" \ 120 "flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \ 121 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ 122 "bootm\0" \ 123 "rootpath=/opt/eldk/ppc_4xx\0" \ 124 "bootfile=/tftpboot/sc3/uImage\0" \ 125 "u-boot=/tftpboot/sc3/u-boot.bin\0" \ 126 "setup=tftp 200000 /tftpboot/sc3/setup.img;source 200000\0" \ 127 "kernel_addr=FFE08000\0" \ 128 "" 129#undef CONFIG_BOOTCOMMAND 130 131#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ 132#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 133 134#if 1 /* feel free to disable for development */ 135#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ 136#define CONFIG_AUTOBOOT_PROMPT \ 137 "\nSC3 - booting... stop with ENTER\n" 138#define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */ 139#define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */ 140#endif 141 142/* 143 * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after 144 * the CONFIG_BOOTDELAY delay to boot your machine 145 */ 146#define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm" 147 148/* 149 * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't 150 * set different values at the u-boot prompt 151 */ 152#ifdef USE_VGA_GRAPHICS 153 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re" 154#else 155 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp" 156#endif 157/* 158 * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT 159 * This reserves memory bank #4 for this purpose 160 */ 161#undef CONFIG_ISP1161_PRESENT 162 163#undef CONFIG_LOADS_ECHO /* no echo on for serial download */ 164#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 165 166#define CONFIG_NET_MULTI 167/* #define CONFIG_EEPRO100_SROM_WRITE */ 168/* #define CONFIG_SHOW_MAC */ 169#define CONFIG_EEPRO100 170 171#define CONFIG_PPC4xx_EMAC 172#define CONFIG_MII 1 /* add 405GP MII PHY management */ 173#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */ 174 175/* 176 * BOOTP options 177 */ 178#define CONFIG_BOOTP_BOOTFILESIZE 179#define CONFIG_BOOTP_BOOTPATH 180#define CONFIG_BOOTP_GATEWAY 181#define CONFIG_BOOTP_HOSTNAME 182 183 184/* 185 * Command line configuration. 186 */ 187#include <config_cmd_default.h> 188 189 190#define CONFIG_CMD_CACHE 191#define CONFIG_CMD_DATE 192#define CONFIG_CMD_DHCP 193#define CONFIG_CMD_ELF 194#define CONFIG_CMD_I2C 195#define CONFIG_CMD_IDE 196#define CONFIG_CMD_IRQ 197#define CONFIG_CMD_JFFS2 198#define CONFIG_CMD_MII 199#define CONFIG_CMD_NAND 200#define CONFIG_CMD_NET 201#define CONFIG_CMD_PCI 202#define CONFIG_CMD_PING 203#define CONFIG_CMD_SOURCE 204 205 206#undef CONFIG_WATCHDOG /* watchdog disabled */ 207 208/* 209 * Miscellaneous configurable options 210 */ 211#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 212#define CONFIG_SYS_PROMPT "SC3> " /* Monitor Command Prompt */ 213#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 214 215#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 216 217#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 218#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 219 220#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 221#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 222 223/* 224 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. 225 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. 226 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. 227 * The Linux BASE_BAUD define should match this configuration. 228 * baseBaud = cpuClock/(uartDivisor*16) 229 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, 230 * set Linux BASE_BAUD to 403200. 231 * 232 * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to 233 * (see 405GP datasheet for descritpion) 234 */ 235#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ 236#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ 237#define CONFIG_SYS_BASE_BAUD 921600 /* internal clock */ 238 239/* The following table includes the supported baudrates */ 240#define CONFIG_SYS_BAUDRATE_TABLE \ 241 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 242 243#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 244#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 245 246#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 247 248/*----------------------------------------------------------------------- 249 * IIC stuff 250 *----------------------------------------------------------------------- 251 */ 252#define CONFIG_HARD_I2C /* I2C with hardware support */ 253#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 254 255#define I2C_INIT 256#define I2C_ACTIVE 0 257#define I2C_TRISTATE 0 258 259#define CONFIG_SYS_I2C_SPEED 100000 /* use the standard 100kHz speed */ 260#define CONFIG_SYS_I2C_SLAVE 0x7F /* mask valid bits */ 261 262#define CONFIG_RTC_DS1337 263#define CONFIG_SYS_I2C_RTC_ADDR 0x68 264 265/*----------------------------------------------------------------------- 266 * PCI stuff 267 *----------------------------------------------------------------------- 268 */ 269#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 270#define PCI_HOST_FORCE 1 /* configure as pci host */ 271#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 272 273#define CONFIG_PCI /* include pci support */ 274#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 275#define CONFIG_PCI_PNP /* do pci plug-and-play */ 276 /* resource configuration */ 277 278/* If you want to see, whats connected to your PCI bus */ 279/* #define CONFIG_PCI_SCAN_SHOW */ 280 281#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ 282#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ 283#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 284#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ 285#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 286#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ 287#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ 288#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 289 290/*----------------------------------------------------------------------- 291 * External peripheral base address 292 *----------------------------------------------------------------------- 293 */ 294#if !defined(CONFIG_CMD_IDE) 295 296#undef CONFIG_IDE_LED /* no led for ide supported */ 297#undef CONFIG_IDE_RESET /* no reset for ide supported */ 298 299/*----------------------------------------------------------------------- 300 * IDE/ATA stuff 301 *----------------------------------------------------------------------- 302 */ 303#else 304#define CONFIG_START_IDE 1 /* check, if use IDE */ 305 306#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 307#undef CONFIG_IDE_LED /* no led for ide supported */ 308#undef CONFIG_IDE_RESET /* no reset for ide supported */ 309 310#define CONFIG_ATAPI 311#define CONFIG_DOS_PARTITION 312#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ 313 314#ifndef IDE_USES_ISA_EMULATION 315 316/* New and faster access */ 317#define CONFIG_SYS_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */ 318 319/* How many IDE busses are available */ 320#define CONFIG_SYS_IDE_MAXBUS 1 321 322/* What IDE ports are available */ 323#define CONFIG_SYS_ATA_IDE0_OFFSET 0x000 /* first is available */ 324#undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */ 325 326/* access to the data port is calculated: 327 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */ 328#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ 329 330/* access to the registers is calculated: 331 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */ 332#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ 333 334/* access to the alternate register is calculated: 335 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */ 336#define CONFIG_SYS_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */ 337 338#else /* IDE_USES_ISA_EMULATION */ 339 340#define CONFIG_SYS_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */ 341 342/* How many IDE busses are available */ 343#define CONFIG_SYS_IDE_MAXBUS 1 344 345/* What IDE ports are available */ 346#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* first is available */ 347#undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */ 348 349/* access to the data port is calculated: 350 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */ 351#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ 352 353/* access to the registers is calculated: 354 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */ 355#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ 356 357/* access to the alternate register is calculated: 358 CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */ 359#define CONFIG_SYS_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */ 360 361#endif /* IDE_USES_ISA_EMULATION */ 362 363#endif 364 365/* 366#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 367#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 368#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 369*/ 370 371/*----------------------------------------------------------------------- 372 * Start addresses for the final memory configuration 373 * (Set up by the startup code) 374 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 375 * 376 * CONFIG_SYS_FLASH_BASE -> start address of internal flash 377 * CONFIG_SYS_MONITOR_BASE -> start of u-boot 378 */ 379#ifndef __ASSEMBLER__ 380extern unsigned long offsetOfBigFlash; 381extern unsigned long offsetOfEnvironment; 382#endif 383 384#define CONFIG_SYS_SDRAM_BASE 0x00000000 385#define CONFIG_SYS_FLASH_BASE 0xFFE00000 386#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 /* placed last 256k */ 387#define CONFIG_SYS_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */ 388#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */ 389 390/* 391 * For booting Linux, the board info and command line data 392 * have to be in the first 8 MiB of memory, since this is 393 * the maximum mapped by the Linux kernel during initialization. 394 */ 395#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 396/*----------------------------------------------------------------------- 397 * FLASH organization ## FIXME: lookup in datasheet 398 */ 399#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 400#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 401 402#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ 403#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ 404#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ 405#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ 406#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 407#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 408#define CONFIG_SYS_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */ 409 410#define CONFIG_ENV_IS_IN_FLASH 1 411#ifdef CONFIG_ENV_IS_IN_FLASH 412#define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */ 413#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 414#define CONFIG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */ 415 416/* Address and size of Redundant Environment Sector */ 417#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 418#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 419 420#endif 421/* let us changing anything in our environment */ 422#define CONFIG_ENV_OVERWRITE 423 424/* 425 * NAND-FLASH stuff 426 */ 427#define CONFIG_SYS_MAX_NAND_DEVICE 1 428#define CONFIG_SYS_NAND_BASE 0x77D00000 429 430#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 431 432#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ 433 434/* No command line, one static partition */ 435#undef CONFIG_CMD_MTDPARTS 436#define CONFIG_JFFS2_DEV "nand0" 437#define CONFIG_JFFS2_PART_SIZE 0x01000000 438#define CONFIG_JFFS2_PART_OFFSET 0x00000000 439 440/* 441 * Init Memory Controller: 442 * 443 */ 444 445#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE 446#define FLASH_BASE1_PRELIM 0 447 448/*----------------------------------------------------------------------- 449 * Some informations about the internal SRAM (OCM=On Chip Memory) 450 * 451 * CONFIG_SYS_OCM_DATA_ADDR -> location 452 * CONFIG_SYS_OCM_DATA_SIZE -> size 453*/ 454 455#define CONFIG_SYS_TEMP_STACK_OCM 1 456#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 457#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 458 459/*----------------------------------------------------------------------- 460 * Definitions for initial stack pointer and data area (in DPRAM): 461 * - we are using the internal 4k SRAM, so we don't need data cache mapping 462 * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR 463 * - Stackpointer will be located to 464 * (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF) 465 * in cpu/ppc4xx/start.S 466 */ 467 468#undef CONFIG_SYS_INIT_DCACHE_CS 469/* Where the internal SRAM starts */ 470#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR 471/* Where the internal SRAM ends (only offset) */ 472#define CONFIG_SYS_INIT_RAM_END 0x0F00 473 474/* 475 476 CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address 477 | | 478 | ^ | 479 | | | 480 | | Stack | 481 CONFIG_SYS_GBL_DATA_OFFSET ----> ------------ 482 | | 483 | 64 Bytes | 484 | | 485 CONFIG_SYS_INIT_RAM_END ------> ------------ higher address 486 (offset only) 487 488*/ 489/* size in bytes reserved for initial data */ 490#define CONFIG_SYS_GBL_DATA_SIZE 64 491#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 492/* Initial value of the stack pointern in internal SRAM */ 493#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 494 495/* 496 * Internal Definitions 497 * 498 * Boot Flags 499 */ 500#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 501#define BOOTFLAG_WARM 0x02 /* Software reboot */ 502 503/* ################################################################################### */ 504/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */ 505/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ 506 507/* This chip select accesses the boot device */ 508/* It depends on boot select switch if this device is 16 or 8 bit */ 509 510#undef CONFIG_SYS_EBC_PB0AP 511#undef CONFIG_SYS_EBC_PB0CR 512 513#undef CONFIG_SYS_EBC_PB1AP 514#undef CONFIG_SYS_EBC_PB1CR 515 516#undef CONFIG_SYS_EBC_PB2AP 517#undef CONFIG_SYS_EBC_PB2CR 518 519#undef CONFIG_SYS_EBC_PB3AP 520#undef CONFIG_SYS_EBC_PB3CR 521 522#undef CONFIG_SYS_EBC_PB4AP 523#undef CONFIG_SYS_EBC_PB4CR 524 525#undef CONFIG_SYS_EBC_PB5AP 526#undef CONFIG_SYS_EBC_PB5CR 527 528#undef CONFIG_SYS_EBC_PB6AP 529#undef CONFIG_SYS_EBC_PB6CR 530 531#undef CONFIG_SYS_EBC_PB7AP 532#undef CONFIG_SYS_EBC_PB7CR 533 534#define CONFIG_SYS_EBC_CFG 0xb84ef000 535 536#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */ 537#undef CONFIG_SPD_EEPROM 538 539/* 540 * Define this to get more information about system configuration 541 */ 542/* #define SC3_DEBUGOUT */ 543#undef SC3_DEBUGOUT 544 545/*********************************************************************** 546 * External peripheral base address 547 ***********************************************************************/ 548 549#define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000 550/* 551 Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu. 552 Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die 553 das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen 554 auf ISA- und PCI-Zyklen) 555 */ 556#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 557/*#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0x79000000 */ 558 559/************************************************************ 560 * Video support 561 ************************************************************/ 562 563#ifdef USE_VGA_GRAPHICS 564#define CONFIG_VIDEO /* To enable video controller support */ 565#define CONFIG_VIDEO_CT69000 566#define CONFIG_CFB_CONSOLE 567/* #define CONFIG_VIDEO_LOGO */ 568#define CONFIG_VGA_AS_SINGLE_DEVICE 569#define CONFIG_VIDEO_SW_CURSOR 570/* #define CONFIG_VIDEO_HW_CURSOR */ 571#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ 572 573#define VIDEO_HW_RECTFILL 574#define VIDEO_HW_BITBLT 575 576#endif 577 578/************************************************************ 579 * Ident 580 ************************************************************/ 581#define CONFIG_SC3_VERSION "r1.4" 582 583#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x) 584 585#endif /* __CONFIG_H */ 586