1/* 2 * (C) Copyright 2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 * Port to AMCC-440SPE Evaluation Board SOP - April 2005 24 * 25 * PCIe supporting routines derived from Linux 440SPe PCIe driver. 26 */ 27 28#include <common.h> 29#include <ppc4xx.h> 30#include <i2c.h> 31#include <netdev.h> 32#include <asm/processor.h> 33#include <asm/io.h> 34#include <asm/4xx_pcie.h> 35#include <asm/errno.h> 36 37#include "yucca.h" 38 39DECLARE_GLOBAL_DATA_PTR; 40 41void fpga_init (void); 42 43#define DEBUG_ENV 44#ifdef DEBUG_ENV 45#define DEBUGF(fmt,args...) printf(fmt ,##args) 46#else 47#define DEBUGF(fmt,args...) 48#endif 49 50#define FALSE 0 51#define TRUE 1 52 53int board_early_init_f (void) 54{ 55/*----------------------------------------------------------------------------+ 56| Define Boot devices 57+----------------------------------------------------------------------------*/ 58#define BOOT_FROM_SMALL_FLASH 0x00 59#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 60#define BOOT_FROM_PCI 0x02 61#define BOOT_DEVICE_UNKNOWN 0x03 62 63/*----------------------------------------------------------------------------+ 64| EBC Devices Characteristics 65| Peripheral Bank Access Parameters - EBC_BxAP 66| Peripheral Bank Configuration Register - EBC_BxCR 67+----------------------------------------------------------------------------*/ 68 69/* 70 * Small Flash and FRAM 71 * BU Value 72 * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 73 * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 74 * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 75 */ 76#define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \ 77 EBC_BXAP_TWT_ENCODE(7) | \ 78 EBC_BXAP_BCE_DISABLE | \ 79 EBC_BXAP_BCT_2TRANS | \ 80 EBC_BXAP_CSN_ENCODE(0) | \ 81 EBC_BXAP_OEN_ENCODE(0) | \ 82 EBC_BXAP_WBN_ENCODE(0) | \ 83 EBC_BXAP_WBF_ENCODE(0) | \ 84 EBC_BXAP_TH_ENCODE(0) | \ 85 EBC_BXAP_RE_DISABLED | \ 86 EBC_BXAP_SOR_DELAYED | \ 87 EBC_BXAP_BEM_WRITEONLY | \ 88 EBC_BXAP_PEN_DISABLED 89 90#define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ 91 EBC_BXCR_BS_16MB | \ 92 EBC_BXCR_BU_RW | \ 93 EBC_BXCR_BW_8BIT 94 95#define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \ 96 EBC_BXCR_BS_16MB | \ 97 EBC_BXCR_BU_RW | \ 98 EBC_BXCR_BW_8BIT 99 100/* 101 * Large Flash and SRAM 102 * BU Value 103 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 104 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 105 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 106*/ 107#define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \ 108 EBC_BXAP_TWT_ENCODE(7) | \ 109 EBC_BXAP_BCE_DISABLE | \ 110 EBC_BXAP_BCT_2TRANS | \ 111 EBC_BXAP_CSN_ENCODE(0) | \ 112 EBC_BXAP_OEN_ENCODE(0) | \ 113 EBC_BXAP_WBN_ENCODE(0) | \ 114 EBC_BXAP_WBF_ENCODE(0) | \ 115 EBC_BXAP_TH_ENCODE(0) | \ 116 EBC_BXAP_RE_DISABLED | \ 117 EBC_BXAP_SOR_DELAYED | \ 118 EBC_BXAP_BEM_WRITEONLY | \ 119 EBC_BXAP_PEN_DISABLED 120 121#define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ 122 EBC_BXCR_BS_16MB | \ 123 EBC_BXCR_BU_RW | \ 124 EBC_BXCR_BW_16BIT 125 126#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \ 127 EBC_BXCR_BS_16MB | \ 128 EBC_BXCR_BU_RW | \ 129 EBC_BXCR_BW_16BIT 130 131/* 132 * FPGA 133 * BU value : 134 * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 135 * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 136 */ 137#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \ 138 EBC_BXAP_TWT_ENCODE(11) | \ 139 EBC_BXAP_BCE_DISABLE | \ 140 EBC_BXAP_BCT_2TRANS | \ 141 EBC_BXAP_CSN_ENCODE(10) | \ 142 EBC_BXAP_OEN_ENCODE(1) | \ 143 EBC_BXAP_WBN_ENCODE(1) | \ 144 EBC_BXAP_WBF_ENCODE(1) | \ 145 EBC_BXAP_TH_ENCODE(1) | \ 146 EBC_BXAP_RE_DISABLED | \ 147 EBC_BXAP_SOR_DELAYED | \ 148 EBC_BXAP_BEM_RW | \ 149 EBC_BXAP_PEN_DISABLED 150 151#define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \ 152 EBC_BXCR_BS_1MB | \ 153 EBC_BXCR_BU_RW | \ 154 EBC_BXCR_BW_16BIT 155 156 unsigned long mfr; 157 /* 158 * Define Variables for EBC initialization depending on BOOTSTRAP option 159 */ 160 unsigned long sdr0_pinstp, sdr0_sdstp1 ; 161 unsigned long bootstrap_settings, ebc_data_width, boot_selection; 162 int computed_boot_device = BOOT_DEVICE_UNKNOWN; 163 164 /*-------------------------------------------------------------------+ 165 | Initialize EBC CONFIG - 166 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC 167 | default value : 168 | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 169 | 170 +-------------------------------------------------------------------*/ 171 mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | 172 EBC_CFG_PTD_ENABLE | 173 EBC_CFG_RTC_16PERCLK | 174 EBC_CFG_ATC_PREVIOUS | 175 EBC_CFG_DTC_PREVIOUS | 176 EBC_CFG_CTC_PREVIOUS | 177 EBC_CFG_OEO_PREVIOUS | 178 EBC_CFG_EMC_DEFAULT | 179 EBC_CFG_PME_DISABLE | 180 EBC_CFG_PR_16); 181 182 /*-------------------------------------------------------------------+ 183 | 184 | PART 1 : Initialize EBC Bank 1 185 | ============================== 186 | Bank1 is always associated to the EPLD. 187 | It has to be initialized prior to other banks settings computation 188 | since some board registers values may be needed to determine the 189 | boot type 190 | 191 +-------------------------------------------------------------------*/ 192 mtebc(PB1AP, EBC_BXAP_FPGA); 193 mtebc(PB1CR, EBC_BXCR_FPGA_CS1); 194 195 /*-------------------------------------------------------------------+ 196 | 197 | PART 2 : Determine which boot device was selected 198 | ================================================= 199 | 200 | Read Pin Strap Register in PPC440SPe 201 | Result can either be : 202 | - Boot strap = boot from EBC 8bits => Small Flash 203 | - Boot strap = boot from PCI 204 | - Boot strap = IIC 205 | In case of boot from IIC, read Serial Device Strap Register1 206 | 207 | Result can either be : 208 | - Boot from EBC - EBC Bus Width = 8bits => Small Flash 209 | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM 210 | - Boot from PCI 211 | 212 +-------------------------------------------------------------------*/ 213 /* Read Pin Strap Register in PPC440SP */ 214 mfsdr(SDR0_PINSTP, sdr0_pinstp); 215 bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK; 216 217 switch (bootstrap_settings) { 218 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0: 219 /* 220 * Strapping Option A 221 * Boot from EBC - 8 bits , Small Flash 222 */ 223 computed_boot_device = BOOT_FROM_SMALL_FLASH; 224 break; 225 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1: 226 /* 227 * Strappping Option B 228 * Boot from PCI 229 */ 230 computed_boot_device = BOOT_FROM_PCI; 231 break; 232 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN: 233 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN: 234 /* 235 * Strapping Option C or D 236 * Boot Settings in IIC EEprom address 0x50 or 0x54 237 * Read Serial Device Strap Register1 in PPC440SPe 238 */ 239 mfsdr(SDR0_SDSTP1, sdr0_sdstp1); 240 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK; 241 ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK; 242 243 switch (boot_selection) { 244 case SDR0_SDSTP1_ERPN_EBC: 245 switch (ebc_data_width) { 246 case SDR0_SDSTP1_EBCW_16_BITS: 247 computed_boot_device = 248 BOOT_FROM_LARGE_FLASH_OR_SRAM; 249 break; 250 case SDR0_SDSTP1_EBCW_8_BITS : 251 computed_boot_device = BOOT_FROM_SMALL_FLASH; 252 break; 253 } 254 break; 255 256 case SDR0_SDSTP1_ERPN_PCI: 257 computed_boot_device = BOOT_FROM_PCI; 258 break; 259 default: 260 /* should not occure */ 261 computed_boot_device = BOOT_DEVICE_UNKNOWN; 262 } 263 break; 264 default: 265 /* should not be */ 266 computed_boot_device = BOOT_DEVICE_UNKNOWN; 267 break; 268 } 269 270 /*-------------------------------------------------------------------+ 271 | 272 | PART 3 : Compute EBC settings depending on selected boot device 273 | ====== ====================================================== 274 | 275 | Resulting EBC init will be among following configurations : 276 | 277 | - Boot from EBC 8bits => boot from Small Flash selected 278 | EBC-CS0 = Small Flash 279 | EBC-CS2 = Large Flash and SRAM 280 | 281 | - Boot from EBC 16bits => boot from Large Flash or SRAM 282 | EBC-CS0 = Large Flash or SRAM 283 | EBC-CS2 = Small Flash 284 | 285 | - Boot from PCI 286 | EBC-CS0 = not initialized to avoid address contention 287 | EBC-CS2 = same as boot from Small Flash selected 288 | 289 +-------------------------------------------------------------------*/ 290 unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; 291 unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; 292 293 switch (computed_boot_device) { 294 /*-------------------------------------------------------------------*/ 295 case BOOT_FROM_PCI: 296 /*-------------------------------------------------------------------*/ 297 /* 298 * By Default CS2 is affected to LARGE Flash 299 * do not initialize SMALL FLASH to avoid address contention 300 * Large Flash 301 */ 302 ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; 303 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; 304 break; 305 306 /*-------------------------------------------------------------------*/ 307 case BOOT_FROM_SMALL_FLASH: 308 /*-------------------------------------------------------------------*/ 309 ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH; 310 ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0; 311 312 /* 313 * Large Flash or SRAM 314 */ 315 /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */ 316 ebc0_cs2_bxap_value = 0x048ff240; 317 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; 318 break; 319 320 /*-------------------------------------------------------------------*/ 321 case BOOT_FROM_LARGE_FLASH_OR_SRAM: 322 /*-------------------------------------------------------------------*/ 323 ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH; 324 ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0; 325 326 /* Small flash */ 327 ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH; 328 ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2; 329 break; 330 331 /*-------------------------------------------------------------------*/ 332 default: 333 /*-------------------------------------------------------------------*/ 334 /* BOOT_DEVICE_UNKNOWN */ 335 break; 336 } 337 338 mtebc(PB0AP, ebc0_cs0_bxap_value); 339 mtebc(PB0CR, ebc0_cs0_bxcr_value); 340 mtebc(PB2AP, ebc0_cs2_bxap_value); 341 mtebc(PB2CR, ebc0_cs2_bxcr_value); 342 343 /*--------------------------------------------------------------------+ 344 | Interrupt controller setup for the AMCC 440SPe Evaluation board. 345 +--------------------------------------------------------------------+ 346 +---------------------------------------------------------------------+ 347 |Interrupt| Source | Pol. | Sensi.| Crit. | 348 +---------+-----------------------------------+-------+-------+-------+ 349 | IRQ 00 | UART0 | High | Level | Non | 350 | IRQ 01 | UART1 | High | Level | Non | 351 | IRQ 02 | IIC0 | High | Level | Non | 352 | IRQ 03 | IIC1 | High | Level | Non | 353 | IRQ 04 | PCI0X0 MSG IN | High | Level | Non | 354 | IRQ 05 | PCI0X0 CMD Write | High | Level | Non | 355 | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | 356 | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | 357 | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | 358 | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | 359 | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | 360 | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | 361 | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | 362 | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | 363 | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | 364 | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | 365 | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | 366 | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | 367 | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | 368 | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | 369 | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | 370 | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | 371 | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | 372 | IRQ 23 | I2O Inbound Doorbell | High | Level | Non | 373 | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | 374 | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | 375 | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | 376 | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | 377 | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | 378 | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | 379 | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | 380 | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | 381 |---------------------------------------------------------------------- 382 | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | 383 | IRQ 33 | MAL Serr | High | Level | Non | 384 | IRQ 34 | MAL Txde | High | Level | Non | 385 | IRQ 35 | MAL Rxde | High | Level | Non | 386 | IRQ 36 | DMC CE or DMC UE | High | Level | Non | 387 | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | 388 | IRQ 38 | MAL TX EOB | High | Level | Non | 389 | IRQ 39 | MAL RX EOB | High | Level | Non | 390 | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | 391 | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | 392 | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | 393 | IRQ 43 | L2 Cache | Risin | Edge | Non | 394 | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | 395 | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | 396 | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | 397 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | 398 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | 399 | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | 400 | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | 401 | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | 402 | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | 403 | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | 404 | IRQ 54 | DMA Error | High | Level | Non | 405 | IRQ 55 | DMA I2O Error | High | Level | Non | 406 | IRQ 56 | Serial ROM | High | Level | Non | 407 | IRQ 57 | PCIX0 Error | High | Edge | Non | 408 | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | 409 | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | 410 | IRQ 60 | EMAC0 Interrupt | High | Level | Non | 411 | IRQ 61 | EMAC0 Wake-up | High | Level | Non | 412 | IRQ 62 | Reserved | High | Level | Non | 413 | IRQ 63 | XOR | High | Level | Non | 414 |---------------------------------------------------------------------- 415 | IRQ 64 | PE0 AL | High | Level | Non | 416 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | 417 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | 418 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | 419 | IRQ 68 | PE0 TCR | High | Level | Non | 420 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | 421 | IRQ 70 | PE0 DCR Error | High | Level | Non | 422 | IRQ 71 | Reserved | N/A | N/A | Non | 423 | IRQ 72 | PE1 AL | High | Level | Non | 424 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | 425 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | 426 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | 427 | IRQ 76 | PE1 TCR | High | Level | Non | 428 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | 429 | IRQ 78 | PE1 DCR Error | High | Level | Non | 430 | IRQ 79 | Reserved | N/A | N/A | Non | 431 | IRQ 80 | PE2 AL | High | Level | Non | 432 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | 433 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | 434 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | 435 | IRQ 84 | PE2 TCR | High | Level | Non | 436 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | 437 | IRQ 86 | PE2 DCR Error | High | Level | Non | 438 | IRQ 87 | Reserved | N/A | N/A | Non | 439 | IRQ 88 | External IRQ(5) | Progr | Progr | Non | 440 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | 441 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | 442 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | 443 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | 444 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | 445 | IRQ 94 | Reserved | N/A | N/A | Non | 446 | IRQ 95 | Reserved | N/A | N/A | Non | 447 |--------------------------------------------------------------------- 448 | IRQ 96 | PE0 INTA | High | Level | Non | 449 | IRQ 97 | PE0 INTB | High | Level | Non | 450 | IRQ 98 | PE0 INTC | High | Level | Non | 451 | IRQ 99 | PE0 INTD | High | Level | Non | 452 | IRQ 100 | PE1 INTA | High | Level | Non | 453 | IRQ 101 | PE1 INTB | High | Level | Non | 454 | IRQ 102 | PE1 INTC | High | Level | Non | 455 | IRQ 103 | PE1 INTD | High | Level | Non | 456 | IRQ 104 | PE2 INTA | High | Level | Non | 457 | IRQ 105 | PE2 INTB | High | Level | Non | 458 | IRQ 106 | PE2 INTC | High | Level | Non | 459 | IRQ 107 | PE2 INTD | Risin | Edge | Non | 460 | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | 461 | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | 462 | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | 463 | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | 464 | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | 465 | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | 466 | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | 467 | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | 468 | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | 469 | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | 470 | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | 471 | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | 472 | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | 473 | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | 474 | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | 475 | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | 476 | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | 477 | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | 478 | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | 479 | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | 480 +---------+-----------------------------------+-------+-------+------*/ 481 /*--------------------------------------------------------------------+ 482 | Put UICs in PowerPC440SPemode. 483 | Initialise UIC registers. Clear all interrupts. Disable all 484 | interrupts. 485 | Set critical interrupt values. Set interrupt polarities. Set 486 | interrupt trigger levels. Make bit 0 High priority. Clear all 487 | interrupts again. 488 +-------------------------------------------------------------------*/ 489 mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ 490 mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ 491 mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical 492 * interrupts */ 493 mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ 494 mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ 495 mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest 496 * priority */ 497 mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */ 498 mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */ 499 500 mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ 501 mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ 502 mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical 503 * interrupts */ 504 mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ 505 mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ 506 mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest 507 * priority */ 508 mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ 509 mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ 510 511 mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ 512 mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ 513 mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical 514 * interrupts */ 515 mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ 516 mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */ 517 mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest 518 * priority */ 519 mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ 520 mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ 521 522 mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ 523 mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted 524 * cascade to be checked */ 525 mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical 526 * interrupts */ 527 mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ 528 mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ 529 mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest 530 * priority */ 531 mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ 532 mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ 533 534 mfsdr(SDR0_MFR, mfr); 535 mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ 536 mtsdr(SDR0_MFR, mfr); 537 538 fpga_init(); 539 540 return 0; 541} 542 543int checkboard (void) 544{ 545 char *s = getenv("serial#"); 546 547 printf("Board: Yucca - AMCC 440SPe Evaluation Board"); 548 if (s != NULL) { 549 puts(", serial# "); 550 puts(s); 551 } 552 putc('\n'); 553 554 return 0; 555} 556 557/* 558 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with 559 * board specific values. 560 */ 561static int ppc440spe_rev_a(void) 562{ 563 if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) 564 return 1; 565 else 566 return 0; 567} 568 569u32 ddr_wrdtr(u32 default_val) { 570 /* 571 * Yucca boards with 440SPe rev. A need a slightly different setup 572 * for the MCIF0_WRDTR register. 573 */ 574 if (ppc440spe_rev_a()) 575 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV); 576 577 return default_val; 578} 579 580u32 ddr_clktr(u32 default_val) { 581 /* 582 * Yucca boards with 440SPe rev. A need a slightly different setup 583 * for the MCIF0_CLKTR register. 584 */ 585 if (ppc440spe_rev_a()) 586 return (SDRAM_CLKTR_CLKP_180_DEG_ADV); 587 588 return default_val; 589} 590 591/************************************************************************* 592 * pci_pre_init 593 * 594 * This routine is called just prior to registering the hose and gives 595 * the board the opportunity to check things. Returning a value of zero 596 * indicates that things are bad & PCI initialization should be aborted. 597 * 598 * Different boards may wish to customize the pci controller structure 599 * (add regions, override default access routines, etc) or perform 600 * certain pre-initialization actions. 601 * 602 ************************************************************************/ 603#if defined(CONFIG_PCI) 604int pci_pre_init(struct pci_controller * hose ) 605{ 606 unsigned long strap; 607 608 /*-------------------------------------------------------------------+ 609 * The yucca board is always configured as the host & requires the 610 * PCI arbiter to be enabled. 611 *-------------------------------------------------------------------*/ 612 mfsdr(SDR0_SDSTP1, strap); 613 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { 614 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); 615 return 0; 616 } 617 618 return 1; 619} 620#endif /* defined(CONFIG_PCI) */ 621 622/************************************************************************* 623 * pci_target_init 624 * 625 * The bootstrap configuration provides default settings for the pci 626 * inbound map (PIM). But the bootstrap config choices are limited and 627 * may not be sufficient for a given board. 628 * 629 ************************************************************************/ 630#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) 631void pci_target_init(struct pci_controller * hose ) 632{ 633 /*-------------------------------------------------------------------+ 634 * Disable everything 635 *-------------------------------------------------------------------*/ 636 out32r( PCIL0_PIM0SA, 0 ); /* disable */ 637 out32r( PCIL0_PIM1SA, 0 ); /* disable */ 638 out32r( PCIL0_PIM2SA, 0 ); /* disable */ 639 out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ 640 641 /*-------------------------------------------------------------------+ 642 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 643 * strapping options to not support sizes such as 128/256 MB. 644 *-------------------------------------------------------------------*/ 645 out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); 646 out32r( PCIL0_PIM0LAH, 0 ); 647 out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); 648 out32r( PCIL0_BAR0, 0 ); 649 650 /*-------------------------------------------------------------------+ 651 * Program the board's subsystem id/vendor id 652 *-------------------------------------------------------------------*/ 653 out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); 654 out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); 655 656 out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); 657} 658#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ 659 660#if defined(CONFIG_PCI) 661/************************************************************************* 662 * is_pci_host 663 * 664 * This routine is called to determine if a pci scan should be 665 * performed. With various hardware environments (especially cPCI and 666 * PPMC) it's insufficient to depend on the state of the arbiter enable 667 * bit in the strap register, or generic host/adapter assumptions. 668 * 669 * Rather than hard-code a bad assumption in the general 440 code, the 670 * 440 pci code requires the board to decide at runtime. 671 * 672 * Return 0 for adapter mode, non-zero for host (monarch) mode. 673 * 674 * 675 ************************************************************************/ 676int is_pci_host(struct pci_controller *hose) 677{ 678 /* The yucca board is always configured as host. */ 679 return 1; 680} 681 682static int yucca_pcie_card_present(int port) 683{ 684 u16 reg; 685 686 reg = in_be16((u16 *)FPGA_REG1C); 687 switch(port) { 688 case 0: 689 return !(reg & FPGA_REG1C_PE0_PRSNT); 690 case 1: 691 return !(reg & FPGA_REG1C_PE1_PRSNT); 692 case 2: 693 return !(reg & FPGA_REG1C_PE2_PRSNT); 694 default: 695 return 0; 696 } 697} 698 699/* 700 * For the given slot, set rootpoint mode, send power to the slot, 701 * turn on the green LED and turn off the yellow LED, enable the clock 702 * and turn off reset. 703 */ 704void yucca_setup_pcie_fpga_rootpoint(int port) 705{ 706 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; 707 708 switch(port) { 709 case 0: 710 rootpoint = FPGA_REG1C_PE0_ROOTPOINT; 711 endpoint = 0; 712 power = FPGA_REG1A_PE0_PWRON; 713 green_led = FPGA_REG1A_PE0_GLED; 714 clock = FPGA_REG1A_PE0_REFCLK_ENABLE; 715 yellow_led = FPGA_REG1A_PE0_YLED; 716 reset_off = FPGA_REG1C_PE0_PERST; 717 break; 718 case 1: 719 rootpoint = 0; 720 endpoint = FPGA_REG1C_PE1_ENDPOINT; 721 power = FPGA_REG1A_PE1_PWRON; 722 green_led = FPGA_REG1A_PE1_GLED; 723 clock = FPGA_REG1A_PE1_REFCLK_ENABLE; 724 yellow_led = FPGA_REG1A_PE1_YLED; 725 reset_off = FPGA_REG1C_PE1_PERST; 726 break; 727 case 2: 728 rootpoint = 0; 729 endpoint = FPGA_REG1C_PE2_ENDPOINT; 730 power = FPGA_REG1A_PE2_PWRON; 731 green_led = FPGA_REG1A_PE2_GLED; 732 clock = FPGA_REG1A_PE2_REFCLK_ENABLE; 733 yellow_led = FPGA_REG1A_PE2_YLED; 734 reset_off = FPGA_REG1C_PE2_PERST; 735 break; 736 737 default: 738 return; 739 } 740 741 out_be16((u16 *)FPGA_REG1A, 742 ~(power | clock | green_led) & 743 (yellow_led | in_be16((u16 *)FPGA_REG1A))); 744 745 out_be16((u16 *)FPGA_REG1C, 746 ~(endpoint | reset_off) & 747 (rootpoint | in_be16((u16 *)FPGA_REG1C))); 748 /* 749 * Leave device in reset for a while after powering on the 750 * slot to give it a chance to initialize. 751 */ 752 udelay(250 * 1000); 753 754 out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C)); 755} 756/* 757 * For the given slot, set endpoint mode, send power to the slot, 758 * turn on the green LED and turn off the yellow LED, enable the clock 759 * .In end point mode reset bit is read only. 760 */ 761void yucca_setup_pcie_fpga_endpoint(int port) 762{ 763 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; 764 765 switch(port) { 766 case 0: 767 rootpoint = FPGA_REG1C_PE0_ROOTPOINT; 768 endpoint = 0; 769 power = FPGA_REG1A_PE0_PWRON; 770 green_led = FPGA_REG1A_PE0_GLED; 771 clock = FPGA_REG1A_PE0_REFCLK_ENABLE; 772 yellow_led = FPGA_REG1A_PE0_YLED; 773 reset_off = FPGA_REG1C_PE0_PERST; 774 break; 775 case 1: 776 rootpoint = 0; 777 endpoint = FPGA_REG1C_PE1_ENDPOINT; 778 power = FPGA_REG1A_PE1_PWRON; 779 green_led = FPGA_REG1A_PE1_GLED; 780 clock = FPGA_REG1A_PE1_REFCLK_ENABLE; 781 yellow_led = FPGA_REG1A_PE1_YLED; 782 reset_off = FPGA_REG1C_PE1_PERST; 783 break; 784 case 2: 785 rootpoint = 0; 786 endpoint = FPGA_REG1C_PE2_ENDPOINT; 787 power = FPGA_REG1A_PE2_PWRON; 788 green_led = FPGA_REG1A_PE2_GLED; 789 clock = FPGA_REG1A_PE2_REFCLK_ENABLE; 790 yellow_led = FPGA_REG1A_PE2_YLED; 791 reset_off = FPGA_REG1C_PE2_PERST; 792 break; 793 794 default: 795 return; 796 } 797 798 out_be16((u16 *)FPGA_REG1A, 799 ~(power | clock | green_led) & 800 (yellow_led | in_be16((u16 *)FPGA_REG1A))); 801 802 out_be16((u16 *)FPGA_REG1C, 803 ~(rootpoint | reset_off) & 804 (endpoint | in_be16((u16 *)FPGA_REG1C))); 805} 806 807static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; 808 809void pcie_setup_hoses(int busno) 810{ 811 struct pci_controller *hose; 812 int i, bus; 813 int ret = 0; 814 char *env; 815 unsigned int delay; 816 817 /* 818 * assume we're called after the PCIX hose is initialized, which takes 819 * bus ID 0 and therefore start numbering PCIe's from 1. 820 */ 821 bus = busno; 822 for (i = 0; i <= 2; i++) { 823 /* Check for yucca card presence */ 824 if (!yucca_pcie_card_present(i)) 825 continue; 826 827 if (is_end_point(i)) { 828 yucca_setup_pcie_fpga_endpoint(i); 829 ret = ppc4xx_init_pcie_endport(i); 830 } else { 831 yucca_setup_pcie_fpga_rootpoint(i); 832 ret = ppc4xx_init_pcie_rootport(i); 833 } 834 if (ret == -ENODEV) 835 continue; 836 if (ret) { 837 printf("PCIE%d: initialization as %s failed\n", i, 838 is_end_point(i) ? "endpoint" : "root-complex"); 839 continue; 840 } 841 842 hose = &pcie_hose[i]; 843 hose->first_busno = bus; 844 hose->last_busno = bus; 845 hose->current_busno = bus; 846 847 /* setup mem resource */ 848 pci_set_region(hose->regions + 0, 849 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, 850 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, 851 CONFIG_SYS_PCIE_MEMSIZE, 852 PCI_REGION_MEM); 853 hose->region_count = 1; 854 pci_register_hose(hose); 855 856 if (is_end_point(i)) { 857 ppc4xx_setup_pcie_endpoint(hose, i); 858 /* 859 * Reson for no scanning is endpoint can not generate 860 * upstream configuration accesses. 861 */ 862 } else { 863 ppc4xx_setup_pcie_rootpoint(hose, i); 864 env = getenv("pciscandelay"); 865 if (env != NULL) { 866 delay = simple_strtoul(env, NULL, 10); 867 if (delay > 5) 868 printf("Warning, expect noticable delay before " 869 "PCIe scan due to 'pciscandelay' value!\n"); 870 mdelay(delay * 1000); 871 } 872 873 /* 874 * Config access can only go down stream 875 */ 876 hose->last_busno = pci_hose_scan(hose); 877 bus = hose->last_busno + 1; 878 } 879 } 880} 881#endif /* defined(CONFIG_PCI) */ 882 883int misc_init_f (void) 884{ 885 uint reg; 886 887 out16(FPGA_REG10, (in16(FPGA_REG10) & 888 ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | 889 FPGA_REG10_10MHZ_ENABLE | 890 FPGA_REG10_100MHZ_ENABLE | 891 FPGA_REG10_GIGABIT_ENABLE | 892 FPGA_REG10_FULL_DUPLEX ); 893 894 udelay(10000); /* wait 10ms */ 895 896 out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH)); 897 898 /* minimal init for PCIe */ 899 /* pci express 0 Endpoint Mode */ 900 mfsdr(SDRN_PESDR_DLPSET(0), reg); 901 reg &= (~0x00400000); 902 mtsdr(SDRN_PESDR_DLPSET(0), reg); 903 /* pci express 1 Rootpoint Mode */ 904 mfsdr(SDRN_PESDR_DLPSET(1), reg); 905 reg |= 0x00400000; 906 mtsdr(SDRN_PESDR_DLPSET(1), reg); 907 /* pci express 2 Rootpoint Mode */ 908 mfsdr(SDRN_PESDR_DLPSET(2), reg); 909 reg |= 0x00400000; 910 mtsdr(SDRN_PESDR_DLPSET(2), reg); 911 912 out16(FPGA_REG1C,(in16 (FPGA_REG1C) & 913 ~FPGA_REG1C_PE0_ROOTPOINT & 914 ~FPGA_REG1C_PE1_ENDPOINT & 915 ~FPGA_REG1C_PE2_ENDPOINT)); 916 917 return 0; 918} 919 920void fpga_init(void) 921{ 922 /* 923 * by default sdram access is disabled by fpga 924 */ 925 out16(FPGA_REG10, (in16 (FPGA_REG10) | 926 FPGA_REG10_SDRAM_ENABLE | 927 FPGA_REG10_ENABLE_DISPLAY )); 928 929 return; 930} 931 932#ifdef CONFIG_POST 933/* 934 * Returns 1 if keys pressed to start the power-on long-running tests 935 * Called from board_init_f(). 936 */ 937int post_hotkeys_pressed(void) 938{ 939 return (ctrlc()); 940} 941#endif 942 943/*---------------------------------------------------------------------------+ 944 | onboard_pci_arbiter_selected => from EPLD 945 +---------------------------------------------------------------------------*/ 946int onboard_pci_arbiter_selected(int core_pci) 947{ 948#if 0 949 unsigned long onboard_pci_arbiter_sel; 950 951 onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK; 952 953 if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL) 954 return (BOARD_OPTION_SELECTED); 955 else 956#endif 957 return (BOARD_OPTION_NOT_SELECTED); 958} 959 960int board_eth_init(bd_t *bis) 961{ 962 cpu_eth_init(bis); 963 return pci_eth_init(bis); 964} 965