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25#include <common.h>
26#include <asm/sizes.h>
27#include <asm/arch/at91sam9263.h>
28#include <asm/arch/at91sam9263_matrix.h>
29#include <asm/arch/at91sam9_smc.h>
30#include <asm/arch/at91_common.h>
31#include <asm/arch/at91_pmc.h>
32#include <asm/arch/at91_rstc.h>
33#include <asm/arch/clk.h>
34#include <asm/arch/gpio.h>
35#include <asm/arch/io.h>
36#include <asm/arch/hardware.h>
37#include <lcd.h>
38#include <atmel_lcdc.h>
39#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
40#include <net.h>
41#endif
42#include <netdev.h>
43
44DECLARE_GLOBAL_DATA_PTR;
45
46
47
48
49
50
51#ifdef CONFIG_CMD_NAND
52static void at91sam9263ek_nand_hw_init(void)
53{
54 unsigned long csa;
55
56
57 csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
58 at91_sys_write(AT91_MATRIX_EBI0CSA,
59 csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
60
61
62 at91_sys_write(AT91_SMC_SETUP(3),
63 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
64 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
65 at91_sys_write(AT91_SMC_PULSE(3),
66 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
67 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
68 at91_sys_write(AT91_SMC_CYCLE(3),
69 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
70 at91_sys_write(AT91_SMC_MODE(3),
71 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
72 AT91_SMC_EXNWMODE_DISABLE |
73#ifdef CONFIG_SYS_NAND_DBW_16
74 AT91_SMC_DBW_16 |
75#else
76 AT91_SMC_DBW_8 |
77#endif
78 AT91_SMC_TDF_(2));
79
80 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
81 1 << AT91SAM9263_ID_PIOCDE);
82
83
84 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
85
86
87 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
88}
89#endif
90
91#ifdef CONFIG_MACB
92static void at91sam9263ek_macb_hw_init(void)
93{
94 unsigned long rstc;
95
96
97 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
98
99
100
101
102
103
104
105
106
107 writel(pin_to_mask(AT91_PIN_PC25),
108 pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
109 writel(pin_to_mask(AT91_PIN_PE25) |
110 pin_to_mask(AT91_PIN_PE26),
111 pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
112
113 rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
114
115
116 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
117 (AT91_RSTC_ERSTL & (0x0D << 8)) |
118 AT91_RSTC_URSTEN);
119
120 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
121
122
123 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
124
125
126 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
127 (rstc) |
128 AT91_RSTC_URSTEN);
129
130
131 writel(pin_to_mask(AT91_PIN_PC25),
132 pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
133 writel(pin_to_mask(AT91_PIN_PE25) |
134 pin_to_mask(AT91_PIN_PE26),
135 pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
136
137 at91_macb_hw_init();
138}
139#endif
140
141#ifdef CONFIG_LCD
142vidinfo_t panel_info = {
143 vl_col: 240,
144 vl_row: 320,
145 vl_clk: 4965000,
146 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
147 ATMEL_LCDC_INVFRAME_INVERTED,
148 vl_bpix: 3,
149 vl_tft: 1,
150 vl_hsync_len: 5,
151 vl_left_margin: 1,
152 vl_right_margin:33,
153 vl_vsync_len: 1,
154 vl_upper_margin:1,
155 vl_lower_margin:0,
156 mmio: AT91SAM9263_LCDC_BASE,
157};
158
159void lcd_enable(void)
160{
161 at91_set_gpio_value(AT91_PIN_PA30, 1);
162}
163
164void lcd_disable(void)
165{
166 at91_set_gpio_value(AT91_PIN_PA30, 0);
167}
168
169static void at91sam9263ek_lcd_hw_init(void)
170{
171 at91_set_A_periph(AT91_PIN_PC1, 0);
172 at91_set_A_periph(AT91_PIN_PC2, 0);
173 at91_set_A_periph(AT91_PIN_PC3, 0);
174 at91_set_B_periph(AT91_PIN_PB9, 0);
175 at91_set_A_periph(AT91_PIN_PC6, 0);
176 at91_set_A_periph(AT91_PIN_PC7, 0);
177 at91_set_A_periph(AT91_PIN_PC8, 0);
178 at91_set_A_periph(AT91_PIN_PC9, 0);
179 at91_set_A_periph(AT91_PIN_PC10, 0);
180 at91_set_A_periph(AT91_PIN_PC11, 0);
181 at91_set_A_periph(AT91_PIN_PC14, 0);
182 at91_set_A_periph(AT91_PIN_PC15, 0);
183 at91_set_A_periph(AT91_PIN_PC16, 0);
184 at91_set_B_periph(AT91_PIN_PC12, 0);
185 at91_set_A_periph(AT91_PIN_PC18, 0);
186 at91_set_A_periph(AT91_PIN_PC19, 0);
187 at91_set_A_periph(AT91_PIN_PC22, 0);
188 at91_set_A_periph(AT91_PIN_PC23, 0);
189 at91_set_A_periph(AT91_PIN_PC24, 0);
190 at91_set_B_periph(AT91_PIN_PC17, 0);
191 at91_set_A_periph(AT91_PIN_PC26, 0);
192 at91_set_A_periph(AT91_PIN_PC27, 0);
193
194 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
195
196 gd->fb_base = AT91SAM9263_SRAM0_BASE;
197}
198
199#ifdef CONFIG_LCD_INFO
200#include <nand.h>
201#include <version.h>
202
203#ifndef CONFIG_SYS_NO_FLASH
204extern flash_info_t flash_info[];
205#endif
206
207void lcd_show_board_info(void)
208{
209 ulong dram_size, nand_size;
210#ifndef CONFIG_SYS_NO_FLASH
211 ulong flash_size;
212#endif
213 int i;
214 char temp[32];
215
216 lcd_printf ("%s\n", U_BOOT_VERSION);
217 lcd_printf ("(C) 2008 ATMEL Corp\n");
218 lcd_printf ("at91support@atmel.com\n");
219 lcd_printf ("%s CPU at %s MHz\n",
220 AT91_CPU_NAME,
221 strmhz(temp, get_cpu_clk_rate()));
222
223 dram_size = 0;
224 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
225 dram_size += gd->bd->bi_dram[i].size;
226 nand_size = 0;
227 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
228 nand_size += nand_info[i].size;
229#ifndef CONFIG_SYS_NO_FLASH
230 flash_size = 0;
231 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
232 flash_size += flash_info[i].size;
233#endif
234 lcd_printf (" %ld MB SDRAM, %ld MB NAND",
235 dram_size >> 20,
236 nand_size >> 20 );
237#ifndef CONFIG_SYS_NO_FLASH
238 lcd_printf (",\n %ld MB NOR",
239 flash_size >> 20);
240#endif
241 lcd_puts ("\n");
242}
243#endif
244#endif
245
246int board_init(void)
247{
248
249 console_init_f();
250
251
252 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
253
254 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
255
256 at91_serial_hw_init();
257#ifdef CONFIG_CMD_NAND
258 at91sam9263ek_nand_hw_init();
259#endif
260#ifdef CONFIG_HAS_DATAFLASH
261 at91_set_gpio_output(AT91_PIN_PE20, 1);
262 at91_spi0_hw_init(1 << 0);
263#endif
264#ifdef CONFIG_MACB
265 at91sam9263ek_macb_hw_init();
266#endif
267#ifdef CONFIG_USB_OHCI_NEW
268 at91_uhp_hw_init();
269#endif
270#ifdef CONFIG_LCD
271 at91sam9263ek_lcd_hw_init();
272#endif
273 return 0;
274}
275
276int dram_init(void)
277{
278 gd->bd->bi_dram[0].start = PHYS_SDRAM;
279 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
280 return 0;
281}
282
283#ifdef CONFIG_RESET_PHY_R
284void reset_phy(void)
285{
286#ifdef CONFIG_MACB
287
288
289
290
291 eth_init(gd->bd);
292#endif
293}
294#endif
295
296int board_eth_init(bd_t *bis)
297{
298 int rc = 0;
299#ifdef CONFIG_MACB
300 rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
301#endif
302 return rc;
303}
304