1/*------------------------------------------------------------------------------+ */ 2/* */ 3/* This source code is dual-licensed. You may use it under the terms */ 4/* of the GNU General Public License version 2, or under the license */ 5/* below. */ 6/* */ 7/* This source code has been made available to you by IBM on an AS-IS */ 8/* basis. Anyone receiving this source is licensed under IBM */ 9/* copyrights to use it in any way he or she deems fit, including */ 10/* copying it, modifying it, compiling it, and redistributing it either */ 11/* with or without modifications. No license under IBM patents or */ 12/* patent applications is to be implied by the copyright license. */ 13/* */ 14/* Any user of this software should understand that IBM cannot provide */ 15/* technical support for this software and will not be responsible for */ 16/* any consequences resulting from the use of this software. */ 17/* */ 18/* Any person who transfers this source code or any derivative work */ 19/* must include the IBM copyright notice, this paragraph, and the */ 20/* preceding two paragraphs in the transferred software. */ 21/* */ 22/* COPYRIGHT I B M CORPORATION 1995 */ 23/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ 24/*------------------------------------------------------------------------------- */ 25 26/*----------------------------------------------------------------------------- */ 27/* Function: ext_bus_cntlr_init */ 28/* Description: Initializes the External Bus Controller for the external */ 29/* peripherals. IMPORTANT: For pass1 this code must run from */ 30/* cache since you can not reliably change a peripheral banks */ 31/* timing register (pbxap) while running code from that bank. */ 32/* For ex., since we are running from ROM on bank 0, we can NOT */ 33/* execute the code that modifies bank 0 timings from ROM, so */ 34/* we run it from cache. */ 35/* Bank 0 - Flash and SRAM */ 36/* Bank 1 - NVRAM/RTC */ 37/* Bank 2 - Keyboard/Mouse controller */ 38/* Bank 3 - IR controller */ 39/* Bank 4 - not used */ 40/* Bank 5 - not used */ 41/* Bank 6 - not used */ 42/* Bank 7 - FPGA registers */ 43/*-----------------------------------------------------------------------------#include <config.h> */ 44#include <ppc4xx.h> 45 46#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 47 48#include <ppc_asm.tmpl> 49#include <ppc_defs.h> 50 51#include <asm/cache.h> 52#include <asm/mmu.h> 53 54/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ 55/* except for #1 which we use for DMA'ing to IOCA-like things, so the */ 56/* control registers to set that up are determined by what we've */ 57/* empirically discovered work there. */ 58 59 .globl ext_bus_cntlr_init 60ext_bus_cntlr_init: 61 mflr r4 /* save link register */ 62 bl ..getAddr 63..getAddr: 64 mflr r3 /* get address of ..getAddr */ 65 mtlr r4 /* restore link register */ 66 addi r4,0,14 /* set ctr to 10; used to prefetch */ 67 mtctr r4 /* 10 cache lines to fit this function */ 68 /* in cache (gives us 8x10=80 instrctns) */ 69..ebcloop: 70 icbt r0,r3 /* prefetch cache line for addr in r3 */ 71 addi r3,r3,32 /* move to next cache line */ 72 bdnz ..ebcloop /* continue for 10 cache lines */ 73 74 /*------------------------------------------------------------------- */ 75 /* Delay to ensure all accesses to ROM are complete before changing */ 76 /* bank 0 timings. 200usec should be enough. */ 77 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ 78 /*------------------------------------------------------------------- */ 79 addis r3,0,0x0 80 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ 81 mtctr r3 82..spinlp: 83 bdnz ..spinlp /* spin loop */ 84 85 86 /*---------------------------------------------------------------------- */ 87 /* Peripheral Bank 0 (Flash) initialization */ 88 /*---------------------------------------------------------------------- */ 89 /* 0x7F8FFE80 slowest boot */ 90 addi r4,0,PB1AP 91 mtdcr EBC0_CFGADDR,r4 92 addis r4,0,0x9B01 93 ori r4,r4,0x5480 94 mtdcr EBC0_CFGDATA,r4 95 96 addi r4,0,PB0CR 97 mtdcr EBC0_CFGADDR,r4 98 addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ 99 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ 100 mtdcr EBC0_CFGDATA,r4 101 102 blr 103 104 /*---------------------------------------------------------------------- */ 105 /* Peripheral Bank 1 (NVRAM/RTC) initialization */ 106 /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ 107 /* and we do DMA on it. The ConfigurationRegister part is threfore */ 108 /* almost arbitrary, except that our linux driver needs to know the */ 109 /* address, but it can query, it.. */ 110 /* */ 111 /* The AccessParameter is CRITICAL, */ 112 /* thouch, since it needs to agree with the electrical timings on the */ 113 /* IOCA parallel interface. That value is: 0x0185,4380 */ 114 /* BurstModeEnable BME=0 */ 115 /* TransferWait TWT=3 */ 116 /* ChipSelectOnTiming CSN=1 */ 117 /* OutputEnableOnTimimg OEN=1 */ 118 /* WriteByteEnableOnTiming WBN=1 */ 119 /* WriteByteEnableOffTiming WBF=0 */ 120 /* TransferHold TH=1 */ 121 /* ReadyEnable RE=1 */ 122 /* SampleOnReady SOR=1 */ 123 /* ByteEnableMode BEM=0 */ 124 /* ParityEnable PEN=0 */ 125 /* all reserved bits=0 */ 126 /*---------------------------------------------------------------------- */ 127 /*---------------------------------------------------------------------- */ 128 addi r4,0,PB1AP 129 mtdcr EBC0_CFGADDR,r4 130 addis r4,0,0x0185 /* hiword */ 131 ori r4,r4,0x4380 /* loword */ 132 mtdcr EBC0_CFGDATA,r4 133 134 addi r4,0,PB1CR 135 mtdcr EBC0_CFGADDR,r4 136 addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ 137 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ 138 mtdcr EBC0_CFGDATA,r4 139 140 blr 141