uboot/board/sc3/sc3.c
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   1/*
   2 * (C) Copyright 2007
   3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
   4 *
   5 * (C) Copyright 2003
   6 * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
   7 * Derived from walnut.c
   8 *
   9 * (C) Copyright 2000
  10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  11 *
  12 * See file CREDITS for list of people who contributed to this
  13 * project.
  14 *
  15 * This program is free software; you can redistribute it and/or
  16 * modify it under the terms of the GNU General Public License as
  17 * published by the Free Software Foundation; either version 2 of
  18 * the License, or (at your option) any later version.
  19 *
  20 * This program is distributed in the hope that it will be useful,
  21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 * GNU General Public License for more details.
  24 *
  25 * You should have received a copy of the GNU General Public License
  26 * along with this program; if not, write to the Free Software
  27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28 * MA 02111-1307 USA
  29 *
  30 * $Log:$
  31 */
  32
  33#include <common.h>
  34#include <asm/processor.h>
  35#include <asm/io.h>
  36#include "sc3.h"
  37#include <pci.h>
  38#include <i2c.h>
  39#include <malloc.h>
  40#include <netdev.h>
  41
  42#undef writel
  43#undef writeb
  44#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
  45#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
  46
  47/* write only register to configure things in our CPLD */
  48#define CPLD_CONTROL_1  0x79000102
  49#define CPLD_VERSION    0x79000103
  50
  51#define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
  52
  53static struct pci_controller hose={0,};
  54
  55/************************************************************
  56 * Standard definition
  57 ************************************************************/
  58
  59/* CPC0_CR0        Function                                 ISA bus
  60        -  GPIO0
  61        -  GPIO1      -> Output: NAND-Command Latch Enable
  62        -  GPIO2      -> Output: NAND Address Latch Enable
  63        -  GPIO3      -> IRQ input                               ISA-IRQ #5 (through CPLD)
  64        -  GPIO4      -> Output: NAND-Chip Enable
  65        -  GPIO5      -> IRQ input                               ISA-IRQ#7 (through CPLD)
  66        -  GPIO6      -> IRQ input                               ISA-IRQ#9 (through CPLD)
  67        -  GPIO7      -> IRQ input                               ISA-IRQ#10 (through CPLD)
  68        -  GPIO8      -> IRQ input                               ISA-IRQ#11 (through CPLD)
  69        -  GPIO9      -> IRQ input                               ISA-IRQ#12 (through CPLD)
  70        - GPIO10/CS1# -> CS1# NAND                               ISA-CS#0
  71        - GPIO11/CS2# -> CS2# ISA emulation                      ISA-CS#1
  72        - GPIO12/CS3# -> CS3# 2nd Flash-Bank                     ISA-CS#2 or ISA-CS#7
  73        - GPIO13/CS4# -> CS4# USB HC or ISA emulation            ISA-CS#3
  74        - GPIO14/CS5# -> CS5# Boosted IDE access                 ISA-CS#4
  75        - GPIO15/CS6# -> CS6# ISA emulation                      ISA-CS#5
  76        - GPIO16/CS7# -> CS7# ISA emulation                      ISA-CS#6
  77        - GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line         ISA-IRQ#3
  78        - GPIO18/IRQ1 -> IRQ input                               ISA-IRQ#14
  79        - GPIO19/IRQ2 -> IRQ input or USB                        ISA-IRQ#4
  80        - GPIO20/IRQ3 -> IRQ input                               PCI-IRQ#D
  81        - GPIO21/IRQ4 -> IRQ input                               PCI-IRQ#C
  82        - GPIO22/IRQ5 -> IRQ input                               PCI-IRQ#B
  83        - GPIO23/IRQ6 -> IRQ input                               PCI-IRQ#A
  84        - GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
  85*/
  86/*
  87| CPLD register: io-space at offset 0x102 (write only)
  88| 0
  89| 1
  90| 2 0=CS#4 USB CS#, 1=ISA or GP bus
  91| 3
  92| 4
  93| 5
  94| 6 1=enable faster IDE access
  95| 7
  96*/
  97#define USB_CHIP_ENABLE 0x04
  98#define IDE_BOOSTING 0x40
  99
 100/* --------------- USB stuff ------------------------------------- */
 101#ifdef CONFIG_ISP1161_PRESENT
 102/**
 103 * initUsbHost- Initialize the Philips isp1161 HC part if present
 104 * @cpldConfig: Pointer to value in write only CPLD register
 105 *
 106 * Initialize the USB host controller if present and fills the
 107 * scratch register to inform the driver about used resources
 108 */
 109
 110static void initUsbHost (unsigned char *cpldConfig)
 111{
 112        int i;
 113        unsigned long usbBase;
 114        /*
 115         * Read back where init.S has located the USB chip
 116         */
 117        mtdcr (0x012, 0x04);
 118        usbBase = mfdcr (0x013);
 119        if (!(usbBase & 0x18000))       /* enabled? */
 120                return;
 121        usbBase &= 0xFFF00000;
 122
 123        /*
 124         * to test for the USB controller enable using of CS#4 and DMA 3 for USB access
 125         */
 126        writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
 127
 128        /*
 129         * first check: is the controller assembled?
 130         */
 131        hcWriteWord (usbBase, 0x5555, HcScratch);
 132        if (hcReadWord (usbBase, HcScratch) == 0x5555) {
 133                hcWriteWord (usbBase, 0xAAAA, HcScratch);
 134                if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
 135                        if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
 136                                return; /* this is not our controller */
 137                /*
 138                 * try a software reset. This needs up to 10 seconds (see datasheet)
 139                 */
 140                        hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
 141                        for (i = 1000; i > 0; i--) {    /* loop up to 10 seconds */
 142                                udelay (10);
 143                                if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
 144                                        break;
 145                        }
 146
 147                        if (!i)
 148                                return;  /* the controller doesn't responding. Broken? */
 149                /*
 150                 * OK. USB controller is ready. Initialize it in such way the later driver
 151                 * can us it (without any knowing about specific implementation)
 152                 */
 153                        hcWriteDWord (usbBase, 0x00000000, HcControl);
 154                /*
 155                 * disable all interrupt sources. Because we
 156                 * don't know where we come from (hard reset, cold start, soft reset...)
 157                 */
 158                        hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
 159                /*
 160                 * our current setup hardware configuration
 161                 * - every port power supply can switched indepently
 162                 * - every port can signal overcurrent
 163                 * - every port is "outside" and the devices are removeable
 164                 */
 165                        hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
 166                        hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
 167                /*
 168                 * don't forget to switch off power supply of each port
 169                 * The later running driver can reenable them to find and use
 170                 * the (maybe) connected devices.
 171                 *
 172                 */
 173                        hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
 174                        hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
 175                        hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
 176                        hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
 177                        hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
 178                        hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
 179                /*
 180                 * controller is present and usable
 181                 */
 182                        *cpldConfig |= USB_CHIP_ENABLE;
 183                }
 184        }
 185}
 186#endif
 187
 188#if defined(CONFIG_START_IDE)
 189int board_start_ide(void)
 190{
 191        if (IS_CAMERON) {
 192                puts ("no IDE on cameron board.\n");
 193                return 0;
 194        }
 195        return 1;
 196}
 197#endif
 198
 199static int sc3_cameron_init (void)
 200{
 201        /* Set up the Memory Controller for the CAMERON version */
 202        mtebc (PB4AP, 0x01805940);
 203        mtebc (PB4CR, 0x7401a000);
 204        mtebc (PB5AP, 0x01805940);
 205        mtebc (PB5CR, 0x7401a000);
 206        mtebc (PB6AP, 0x0);
 207        mtebc (PB6CR, 0x0);
 208        mtebc (PB7AP, 0x0);
 209        mtebc (PB7CR, 0x0);
 210        return 0;
 211}
 212
 213void sc3_read_eeprom (void)
 214{
 215        uchar i2c_buffer[18];
 216
 217        i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
 218        i2c_buffer[9] = 0;
 219        setenv ("serial#", (char *)i2c_buffer);
 220
 221        /* read mac-address from eeprom */
 222        i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
 223        i2c_buffer[17] = 0;
 224        i2c_buffer[16] = i2c_buffer[14];
 225        i2c_buffer[15] = i2c_buffer[13];
 226        i2c_buffer[14] = ':';
 227        i2c_buffer[13] = i2c_buffer[12];
 228        i2c_buffer[12] = i2c_buffer[11];
 229        i2c_buffer[11] = ':';
 230        i2c_buffer[8] = ':';
 231        i2c_buffer[5] = ':';
 232        i2c_buffer[2] = ':';
 233        setenv ("ethaddr", (char *)i2c_buffer);
 234}
 235
 236int board_early_init_f (void)
 237{
 238        /* write only register to configure things in our CPLD */
 239        unsigned char cpldConfig_1=0x00;
 240
 241/*-------------------------------------------------------------------------+
 242| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
 243|
 244| Note: IRQ 0  UART 0, active high; level sensitive
 245|       IRQ 1  UART 1, active high; level sensitive
 246|       IRQ 2  IIC, active high; level sensitive
 247|       IRQ 3  Ext. master, rising edge, edge sensitive
 248|       IRQ 4  PCI, active high; level sensitive
 249|       IRQ 5  DMA Channel 0, active high; level sensitive
 250|       IRQ 6  DMA Channel 1, active high; level sensitive
 251|       IRQ 7  DMA Channel 2, active high; level sensitive
 252|       IRQ 8  DMA Channel 3, active high; level sensitive
 253|       IRQ 9  Ethernet Wakeup, active high; level sensitive
 254|       IRQ 10 MAL System Error (SERR), active high; level sensitive
 255|       IRQ 11 MAL Tx End of Buffer, active high; level sensitive
 256|       IRQ 12 MAL Rx End of Buffer, active high; level sensitive
 257|       IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
 258|       IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
 259|       IRQ 15 Ethernet, active high; level sensitive
 260|       IRQ 16 External PCI SERR, active high; level sensitive
 261|       IRQ 17 ECC Correctable Error, active high; level sensitive
 262|       IRQ 18 PCI Power Management, active high; level sensitive
 263|
 264|       IRQ 19 (EXT IRQ7 405GPr only)
 265|       IRQ 20 (EXT IRQ8 405GPr only)
 266|       IRQ 21 (EXT IRQ9 405GPr only)
 267|       IRQ 22 (EXT IRQ10 405GPr only)
 268|       IRQ 23 (EXT IRQ11 405GPr only)
 269|       IRQ 24 (EXT IRQ12 405GPr only)
 270|
 271|       IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
 272|       IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
 273|       IRQ 27 (EXT IRQ 2) USB controller
 274|       IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
 275|       IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
 276|       IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
 277|       IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
 278|
 279| Direct Memory Access Controller Signal Polarities
 280|       DRQ0 active high (like ISA)
 281|       ACK0 active low (like ISA)
 282|       EOT0 active high (like ISA)
 283|       DRQ1 active high (like ISA)
 284|       ACK1 active low (like ISA)
 285|       EOT1 active high (like ISA)
 286|       DRQ2 active high (like ISA)
 287|       ACK2 active low (like ISA)
 288|       EOT2 active high (like ISA)
 289|       DRQ3 active high (like ISA)
 290|       ACK3 active low (like ISA)
 291|       EOT3 active high (like ISA)
 292|
 293+-------------------------------------------------------------------------*/
 294
 295        writeb (cpldConfig_1, CPLD_CONTROL_1);  /* disable everything in CPLD */
 296
 297        mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
 298        mtdcr (UIC0ER, 0x00000000);    /* disable all ints */
 299        mtdcr (UIC0CR, 0x00000000);    /* set all to be non-critical */
 300
 301        if (IS_CAMERON) {
 302                sc3_cameron_init();
 303                mtdcr (0x0B6, 0x18000000);
 304                mtdcr (UIC0PR, 0xFFFFFFF0);
 305                mtdcr (UIC0TR, 0x10001030);
 306        } else {
 307                mtdcr (0x0B6, 0x0000000);
 308                mtdcr (UIC0PR, 0xFFFFFFE0);
 309                mtdcr (UIC0TR, 0x10000020);
 310        }
 311        mtdcr (UIC0VCR, 0x00000001);   /* set vect base=0,INT0 highest priority */
 312        mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
 313
 314        /* setup other implementation specific details */
 315        mtdcr (CPC0_ECR, 0x60606000);
 316
 317        mtdcr (CPC0_CR1, 0x000042C0);
 318
 319        if (IS_CAMERON) {
 320                mtdcr (CPC0_CR0, 0x01380000);
 321                /* Setup the GPIOs */
 322                writel (0x08008000, 0xEF600700);        /* Output states */
 323                writel (0x00000000, 0xEF600718);        /* Open Drain control */
 324                writel (0x68098000, 0xEF600704);        /* Output control */
 325        } else {
 326                mtdcr (CPC0_CR0,0x00080000);
 327                /* Setup the GPIOs */
 328                writel (0x08000000, 0xEF600700);        /* Output states */
 329                writel (0x14000000, 0xEF600718);        /* Open Drain control */
 330                writel (0x7C000000, 0xEF600704);        /* Output control */
 331        }
 332
 333        /* Code decompression disabled */
 334        mtdcr (KIAR, KCONF);
 335        mtdcr (KIDR, 0x2B);
 336
 337        /* CPC0_ER: enable sleep mode of (currently) unused components */
 338        /* CPC0_FR: force unused components into sleep mode */
 339        mtdcr (CPMER, 0x3F800000);
 340        mtdcr (CPMFR, 0x14000000);
 341
 342        /* set PLB priority */
 343        mtdcr (0x87, 0x08000000);
 344
 345        /* --------------- DMA stuff ------------------------------------- */
 346        mtdcr (0x126, 0x49200000);
 347
 348#ifndef IDE_USES_ISA_EMULATION
 349        cpldConfig_1 |= IDE_BOOSTING;   /* enable faster IDE */
 350        /* cpldConfig |= 0x01; */       /* enable 8.33MHz output, if *not* present on your baseboard */
 351        writeb (cpldConfig_1, CPLD_CONTROL_1);
 352#endif
 353
 354#ifdef CONFIG_ISP1161_PRESENT
 355        initUsbHost (&cpldConfig_1);
 356        writeb (cpldConfig_1, CPLD_CONTROL_1);
 357#endif
 358        /* FIXME: for what must we do this */
 359        *(unsigned long *)0x79000080 = 0x0001;
 360        return(0);
 361}
 362
 363int misc_init_r (void)
 364{
 365        char *s1;
 366        int i, xilinx_val;
 367        volatile char *xilinx_adr;
 368        xilinx_adr = (char *)0x79000102;
 369
 370        *xilinx_adr = 0x00;
 371
 372/* customer settings ***************************************** */
 373/*
 374        s1 = getenv ("function");
 375        if (s1) {
 376                if (!strcmp (s1, "Rosho")) {
 377                        printf ("function 'Rosho' activated\n");
 378                        *xilinx_adr = 0x40;
 379                }
 380                else {
 381                        printf (">>>>>>>>>> function %s not recognized\n",s1);
 382                }
 383        }
 384*/
 385
 386/* individual settings ***************************************** */
 387        if ((s1 = getenv ("xilinx"))) {
 388                i=0;
 389                xilinx_val = 0;
 390                while (i < 3 && s1[i]) {
 391                        if (s1[i] >= '0' && s1[i] <= '9')
 392                                xilinx_val = (xilinx_val << 4) + s1[i] - '0';
 393                        else
 394                                if (s1[i] >= 'A' && s1[i] <= 'F')
 395                                        xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
 396                                else
 397                                        if (s1[i] >= 'a' && s1[i] <= 'f')
 398                                                xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
 399                                        else {
 400                                                xilinx_val = -1;
 401                                                break;
 402                                        }
 403                        i++;
 404                }
 405                if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
 406                        printf ("Xilinx: set to %s\n", s1);
 407                        *xilinx_adr = (unsigned char) xilinx_val;
 408                } else
 409                        printf ("Xilinx: rejected value %s\n", s1);
 410        }
 411        return 0;
 412}
 413
 414/* -------------------------------------------------------------------------
 415 * printCSConfig
 416 *
 417 * Print some informations about chips select configurations
 418 * Only used while debugging.
 419 *
 420 * Params:
 421 * - No. of CS pin
 422 * - AP of this CS
 423 * - CR of this CS
 424 *
 425 * Returns
 426 * nothing
 427   ------------------------------------------------------------------------- */
 428
 429#ifdef SC3_DEBUGOUT
 430static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
 431{
 432        const char *bsize[4] = {"8","16","32","?"};
 433        const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
 434        const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
 435
 436#define CYCLE 30  /* time of one clock (based on 33MHz) */
 437
 438        printf("\nCS#%d",reg);
 439        if (!(cr & 0x00018000))
 440                puts(" unused");
 441        else {
 442                if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
 443                        puts(" Address is not multiple of bank size!");
 444
 445                printf("\n -%s bit device",
 446                        bsize[(cr & 0x00006000) >> 13]);
 447                printf(" at 0x%08lX", cr & 0xFFF00000U);
 448                printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
 449                printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
 450                if (ap & 0x80000000) {
 451                        printf("\n -Burst device (%luns/%luns)",
 452                                (((ap & 0x7C000000) >> 26) + 1) * CYCLE,
 453                                (((ap & 0x03800000) >> 23) + 1) * CYCLE);
 454                } else {
 455                        printf("\n -Non burst device, active cycle %luns",
 456                                (((ap & 0x7F800000) >> 23) + 1) * CYCLE);
 457                        printf("\n -Address setup %luns",
 458                                ((ap & 0xC0000) >> 18) * CYCLE);
 459                        printf("\n -CS active to RD %luns/WR %luns",
 460                                ((ap & 0x30000) >> 16) * CYCLE,
 461                                ((ap & 0xC000) >> 14) * CYCLE);
 462                        printf("\n -WR to CS inactive %luns",
 463                                ((ap & 0x3000) >> 12) * CYCLE);
 464                        printf("\n -Hold after access %luns",
 465                                ((ap & 0xE00) >> 9) * CYCLE);
 466                        printf("\n -Ready is %sabled",
 467                                ap & 0x100 ? "en" : "dis");
 468                }
 469        }
 470}
 471#endif
 472
 473#ifdef SC3_DEBUGOUT
 474
 475static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP,
 476                                PB5AP, PB6AP, PB7AP};
 477static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR,
 478                                PB5CR, PB6CR, PB7CR};
 479
 480static int show_reg (int nr)
 481{
 482        unsigned long ul1, ul2;
 483
 484        mtdcr (EBC0_CFGADDR, ap[nr]);
 485        ul1 = mfdcr (EBC0_CFGDATA);
 486        mtdcr (EBC0_CFGADDR, cr[nr]);
 487        ul2 = mfdcr(EBC0_CFGDATA);
 488        printCSConfig(nr, ul1, ul2);
 489        return 0;
 490}
 491#endif
 492
 493int checkboard (void)
 494{
 495#ifdef SC3_DEBUGOUT
 496        unsigned long ul1;
 497        int     i;
 498
 499        for (i = 0; i < 8; i++) {
 500                show_reg (i);
 501        }
 502
 503        mtdcr (EBC0_CFGADDR, EBC0_CFG);
 504        ul1 = mfdcr (EBC0_CFGDATA);
 505
 506        puts ("\nGeneral configuration:\n");
 507
 508        if (ul1 & 0x80000000)
 509                printf(" -External Bus is always driven\n");
 510
 511        if (ul1 & 0x400000)
 512                printf(" -CS signals are always driven\n");
 513
 514        if (ul1 & 0x20000)
 515                printf(" -PowerDown after %lu clocks\n",
 516                        (ul1 & 0x1F000) >> 7);
 517
 518        switch (ul1 & 0xC0000)
 519        {
 520        case 0xC0000:
 521                printf(" -No external master present\n");
 522                break;
 523        case 0x00000:
 524                printf(" -8 bit external master present\n");
 525                break;
 526        case 0x40000:
 527                printf(" -16 bit external master present\n");
 528                break;
 529        case 0x80000:
 530                printf(" -32 bit external master present\n");
 531                break;
 532        }
 533
 534        switch (ul1 & 0x300000)
 535        {
 536        case 0x300000:
 537                printf(" -Prefetch: Illegal setting!\n");
 538                break;
 539        case 0x000000:
 540                printf(" -1 doubleword prefetch\n");
 541                break;
 542        case 0x100000:
 543                printf(" -2 doublewords prefetch\n");
 544                break;
 545        case 0x200000:
 546                printf(" -4 doublewords prefetch\n");
 547                break;
 548        }
 549        putc ('\n');
 550#endif
 551        printf("Board: SolidCard III %s %s version.\n",
 552                (IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
 553        return 0;
 554}
 555
 556static int printSDRAMConfig(char reg, unsigned long cr)
 557{
 558        const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
 559#ifdef SC3_DEBUGOUT
 560        const char *basize[8]=
 561                {"4", "8", "16", "32", "64", "128", "256", "Reserved"};
 562
 563        printf("SDRAM bank %d",reg);
 564
 565        if (!(cr & 0x01))
 566                puts(" disabled\n");
 567        else {
 568                printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
 569                printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
 570        }
 571#endif
 572
 573        if (cr & 0x01)
 574                return(bisize[(cr & 0xE0000) >> 17]);
 575
 576        return 0;
 577}
 578
 579#ifdef SC3_DEBUGOUT
 580static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR};
 581#endif
 582
 583phys_size_t initdram (int board_type)
 584{
 585        unsigned int mems=0;
 586        unsigned long ul1;
 587
 588#ifdef SC3_DEBUGOUT
 589        unsigned long ul2;
 590        int     i;
 591
 592        puts("\nSDRAM configuration:\n");
 593
 594        mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 595        ul1 = mfdcr(SDRAM0_CFGDATA);
 596
 597        if (!(ul1 & 0x80000000)) {
 598                puts(" Controller disabled\n");
 599                return 0;
 600        }
 601        for (i = 0; i < 4; i++) {
 602                mtdcr (SDRAM0_CFGADDR, mbcf[i]);
 603                ul1 = mfdcr (SDRAM0_CFGDATA);
 604                mems += printSDRAMConfig (i, ul1);
 605        }
 606
 607        mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
 608        ul1 = mfdcr(SDRAM0_CFGDATA);
 609
 610        printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
 611        printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
 612        printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
 613        printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
 614        printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
 615        printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
 616        puts ("Misc:\n");
 617        mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
 618        ul1 = mfdcr(SDRAM0_CFGDATA);
 619        printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
 620
 621        mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT);
 622        ul2=mfdcr(SDRAM0_CFGDATA);
 623
 624        mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG);
 625        ul1=mfdcr(SDRAM0_CFGDATA);
 626
 627        if (ul1 & 0x20000000)
 628                printf(" -Power Down after: %luns\n",
 629                        ((ul2 & 0xFFC00000) >> 22) * 7);
 630        else
 631                puts(" -Power Down disabled\n");
 632
 633        if (ul1 & 0x40000000)
 634                printf(" -Self refresh feature active\n");
 635        else
 636                puts(" -Self refresh disabled\n");
 637
 638        if (ul1 & 0x10000000)
 639                puts(" -ECC enabled\n");
 640        else
 641                puts(" -ECC disabled\n");
 642
 643        if (ul1 & 0x8000000)
 644                puts(" -Using registered SDRAM\n");
 645
 646        if (!(ul1 & 0x6000000))
 647                puts(" -Using 32 bit data width\n");
 648        else
 649                puts(" -Illegal data width!\n");
 650
 651        if (ul1 & 0x400000)
 652                puts(" -ECC drivers inactive\n");
 653        else
 654                puts(" -ECC drivers active\n");
 655
 656        if (ul1 & 0x200000)
 657                puts(" -Memory lines always active outputs\n");
 658        else
 659                puts(" -Memory lines only at write cycles active outputs\n");
 660
 661        mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS);
 662        ul1 = mfdcr (SDRAM0_CFGDATA);
 663        if (ul1 & 0x80000000)
 664                puts(" -SDRAM Controller ready\n");
 665        else
 666                puts(" -SDRAM Controller not ready\n");
 667
 668        if (ul1 & 0x4000000)
 669                puts(" -SDRAM in self refresh mode!\n");
 670
 671        return (mems * 1024 * 1024);
 672#else
 673        mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 674        ul1 = mfdcr (SDRAM0_CFGDATA);
 675        mems = printSDRAMConfig (0, ul1);
 676
 677        mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
 678        ul1 = mfdcr (SDRAM0_CFGDATA);
 679        mems += printSDRAMConfig (1, ul1);
 680
 681        mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
 682        ul1 = mfdcr(SDRAM0_CFGDATA);
 683        mems += printSDRAMConfig (2, ul1);
 684
 685        mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
 686        ul1 = mfdcr(SDRAM0_CFGDATA);
 687        mems += printSDRAMConfig (3, ul1);
 688
 689        return (mems * 1024 * 1024);
 690#endif
 691}
 692
 693static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 694{
 695/*-------------------------------------------------------------------------+
 696 |             ,-.     ,-.        ,-.        ,-.        ,-.
 697 |   INTD# ----|B|-----|P|-.    ,-|P|-.    ,-| |-.    ,-|G|
 698 |             |R|     |C|  \  /  |C|  \  /  |E|  \  /  |r|
 699 |   INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
 700 |             |D|     |0|  \/    |0|  \/    |h|  \/    |f|
 701 |   INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
 702 |             |E|     |+| /\     |+| /\     |r| /\     |k|
 703 |   INTA# ----| |-----| |-  `----| |-  `----| |-  `----| |
 704 |             `-'     `-'        `-'        `-'        `-'
 705 |   Slot      0       10         11         12         13
 706 |   REQ#              0          1          2          *
 707 |   GNT#              0          1          2          *
 708 +-------------------------------------------------------------------------*/
 709        unsigned char int_line = 0xff;
 710
 711        switch (PCI_DEV(dev)) {
 712        case 10:
 713                int_line = 31; /* INT A */
 714                POST_OUT(0x42);
 715                break;
 716
 717        case 11:
 718                int_line = 30; /* INT B */
 719                POST_OUT(0x43);
 720                break;
 721
 722        case 12:
 723                int_line = 29; /* INT C */
 724                POST_OUT(0x44);
 725                break;
 726
 727        case 13:
 728                int_line = 28; /* INT D */
 729                POST_OUT(0x45);
 730                break;
 731        }
 732        pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
 733}
 734
 735extern void pci_405gp_init(struct pci_controller *hose);
 736extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
 737extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
 738/*
 739 * The following table is used when there is a special need to setup a PCI device.
 740 * For every PCI device found in this table is called the given init function with given
 741 * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
 742 * parameters!
 743 *
 744*/
 745static struct pci_config_table pci_solidcard3_config_table[] =
 746{
 747/* Host to PCI Bridge device (405GP) */
 748        {
 749                vendor: 0x1014,
 750                device: 0x0156,
 751                class: PCI_CLASS_BRIDGE_HOST,
 752                bus: 0,
 753                dev: 0,
 754                func: 0,
 755                config_device: pci_405gp_setup_bridge
 756        },
 757        { }
 758};
 759
 760/*-------------------------------------------------------------------------+
 761 | pci_init_board (Called from pci_init() in drivers/pci/pci.c)
 762 |
 763 | Init the PCI part of the SolidCard III
 764 |
 765 | Params:
 766 * - Pointer to current PCI hose
 767 * - Current Device
 768 *
 769 * Returns
 770 * nothing
 771 +-------------------------------------------------------------------------*/
 772
 773void pci_init_board(void)
 774{
 775        POST_OUT(0x41);
 776/*
 777 * we want the ptrs to RAM not flash (ie don't use init list)
 778 */
 779        hose.fixup_irq    = pci_solidcard3_fixup_irq;
 780        hose.config_table = pci_solidcard3_config_table;
 781        pci_405gp_init(&hose);
 782}
 783
 784int board_eth_init(bd_t *bis)
 785{
 786        return pci_eth_init(bis);
 787}
 788