LXR uboot/cpu/blackfin/cpu.c

   1/*
   2 * U-boot - cpu.c CPU specific functions
   3 *
   4 * Copyright (c) 2005-2008 Analog Devices Inc.
   5 *
   6 * (C) Copyright 2000-2004
   7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8 *
   9 * Licensed under the GPL-2 or later.
  10 */
  11
  12#include <common.h>
  13#include <command.h>
  14#include <asm/blackfin.h>
  15#include <asm/cplb.h>
  16#include <asm/mach-common/bits/core.h>
  17#include <asm/mach-common/bits/ebiu.h>
  18#include <asm/mach-common/bits/trace.h>
  19
  20#include "cpu.h"
  21#include "serial.h"
  22
  23ulong bfin_poweron_retx;
  24
  25__attribute__ ((__noreturn__))
  26void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
  27{
  28        extern char _stext_l1;
  29#ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
  30        /* Build a NOP slide over the LDR jump block.  Whee! */
  31        char nops[0xC];
  32        serial_early_puts("NOP Slide\n");
  33        memset(nops, 0x00, sizeof(nops));
  34        memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops));
  35#endif
  36
  37        if (!loaded_from_ldr) {
  38                /* Relocate sections into L1 if the LDR didn't do it -- don't
  39                 * check length because the linker script does the size
  40                 * checking at build time.
  41                 */
  42                serial_early_puts("L1 Relocate\n");
  43                extern char _stext_l1, _etext_l1, _stext_l1_lma;
  44                memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1));
  45                extern char _sdata_l1, _edata_l1, _sdata_l1_lma;
  46                memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1));
  47        }
  48#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
  49        /* The BF537 bootrom will reset the EBIU_AMGCTL register on us
  50         * after it has finished loading the LDR.  So configure it again.
  51         */
  52        else
  53                bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
  54#endif
  55
  56        /* Save RETX so we can pass it while booting Linux */
  57        bfin_poweron_retx = bootflag;
  58
  59#ifdef CONFIG_DEBUG_DUMP
  60        /* Turn on hardware trace buffer */
  61        bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
  62#endif
  63
  64#ifndef CONFIG_PANIC_HANG
  65        /* Reset upon a double exception rather than just hanging.
  66         * Do not do bfin_read on SWRST as that will reset status bits.
  67         */
  68        bfin_write_SWRST(DOUBLE_FAULT);
  69#endif
  70
  71        serial_early_puts("Board init flash\n");
  72        board_init_f(bootflag);
  73}
  74
  75int exception_init(void)
  76{
  77        bfin_write_EVT3(trap);
  78        return 0;
  79}
  80
  81int irq_init(void)
  82{
  83#ifdef SIC_IMASK0
  84        bfin_write_SIC_IMASK0(0);
  85        bfin_write_SIC_IMASK1(0);
  86# ifdef SIC_IMASK2
  87        bfin_write_SIC_IMASK2(0);
  88# endif
  89#elif defined(SICA_IMASK0)
  90        bfin_write_SICA_IMASK0(0);
  91        bfin_write_SICA_IMASK1(0);
  92#else
  93        bfin_write_SIC_IMASK(0);
  94#endif
  95        bfin_write_EVT2(evt_default);   /* NMI */
  96        bfin_write_EVT5(evt_default);   /* hardware error */
  97        bfin_write_EVT6(evt_default);   /* core timer */
  98        bfin_write_EVT7(evt_default);
  99        bfin_write_EVT8(evt_default);
 100        bfin_write_EVT9(evt_default);
 101        bfin_write_EVT10(evt_default);
 102        bfin_write_EVT11(evt_default);
 103        bfin_write_EVT12(evt_default);
 104        bfin_write_EVT13(evt_default);
 105        bfin_write_EVT14(evt_default);
 106        bfin_write_EVT15(evt_default);
 107        bfin_write_ILAT(0);
 108        CSYNC();
 109        /* enable hardware error irq */
 110        irq_flags = 0x3f;
 111        local_irq_enable();
 112        return 0;
 113}
 114