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20#include <common.h>
21#include <linux/types.h>
22#include <asm/traps.h>
23#include <asm/cplb.h>
24#include <asm/io.h>
25#include <asm/mach-common/bits/core.h>
26#include <asm/mach-common/bits/mpu.h>
27#include <asm/mach-common/bits/trace.h>
28#include "cpu.h"
29
30#define trace_buffer_save(x) \
31 do { \
32 (x) = bfin_read_TBUFCTL(); \
33 bfin_write_TBUFCTL((x) & ~TBUFEN); \
34 } while (0)
35
36#define trace_buffer_restore(x) \
37 bfin_write_TBUFCTL((x))
38
39
40
41
42
43
44
45
46
47struct memory_map {
48 uint32_t start, end;
49 uint32_t data_flags, inst_flags;
50};
51const struct memory_map const bfin_memory_map[] = {
52 {
53 .start = 0x00000000,
54 .end = 0x20000000,
55 .data_flags = SDRAM_DGENERIC,
56 .inst_flags = SDRAM_IGENERIC,
57 },
58 {
59 .start = 0x20000000,
60 .end = 0x30000000,
61 .data_flags = SDRAM_EBIU,
62 .inst_flags = SDRAM_INON_CHBL,
63 },
64 {
65 .start = 0xE0000000,
66 .end = 0xFFFFFFFF,
67 .data_flags = L1_DMEMORY,
68 .inst_flags = L1_IMEMORY,
69 }
70};
71
72void trap_c(struct pt_regs *regs)
73{
74 uint32_t trapnr = (regs->seqstat & EXCAUSE);
75 bool data = false;
76
77 switch (trapnr) {
78
79 case VEC_CPLB_M:
80
81 if (ANOMALY_05000261) {
82 static uint32_t last_cplb_fault_retx;
83
84
85
86
87
88 if (last_cplb_fault_retx != regs->retx) {
89 last_cplb_fault_retx = regs->retx;
90 return;
91 }
92 }
93
94 data = true;
95
96
97
98 case VEC_CPLB_I_M: {
99 volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
100 uint32_t new_cplb_addr = 0, new_cplb_data = 0;
101 static size_t last_evicted;
102 size_t i;
103
104 new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
105
106 for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
107
108 if (new_cplb_addr >= bfin_memory_map[i].start &&
109 new_cplb_addr < bfin_memory_map[i].end)
110 break;
111 }
112 if (i == ARRAY_SIZE(bfin_memory_map)) {
113 printf("%cCPLB exception outside of memory map at 0x%p\n",
114 (data ? 'D' : 'I'), (void *)new_cplb_addr);
115 bfin_panic(regs);
116 } else
117 debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end);
118 new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
119
120 if (data) {
121 CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
122 CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
123 } else {
124 CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
125 CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
126 }
127
128
129 i = last_evicted & 0xF;
130 debug("last evicted = %i\n", i);
131 CPLB_DATA = CPLB_DATA_BASE + i;
132 while (*CPLB_DATA & CPLB_LOCK) {
133 debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
134 i = (i + 1) & 0xF;
135 CPLB_DATA = CPLB_DATA_BASE + i;
136 }
137 CPLB_ADDR = CPLB_ADDR_BASE + i;
138
139 debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA);
140 last_evicted = i + 1;
141
142
143#if ENDCPLB != ENICPLB
144# error cplb enable bit violates my sanity
145#endif
146 uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
147 bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
148 *CPLB_ADDR = new_cplb_addr;
149 *CPLB_DATA = new_cplb_data;
150 bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
151 SSYNC();
152
153
154 CPLB_ADDR = CPLB_ADDR_BASE;
155 CPLB_DATA = CPLB_DATA_BASE;
156 for (i = 0; i < 16; ++i)
157 debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
158
159 break;
160 }
161
162 default:
163
164 bfin_panic(regs);
165 }
166}
167
168#ifdef CONFIG_DEBUG_DUMP
169# define ENABLE_DUMP 1
170#else
171# define ENABLE_DUMP 0
172#endif
173
174#ifndef CONFIG_KALLSYMS
175const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
176{
177 *caddr = addr;
178 return "N/A";
179}
180#endif
181
182static void decode_address(char *buf, unsigned long address)
183{
184 unsigned long sym_addr;
185 void *paddr = (void *)address;
186 const char *sym = symbol_lookup(address, &sym_addr);
187
188 if (sym) {
189 sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr);
190 return;
191 }
192
193 if (!address)
194 sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
195 else if (address >= CONFIG_SYS_MONITOR_BASE &&
196 address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
197 sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
198 else
199 sprintf(buf, "<0x%p> /* unknown address */", paddr);
200}
201
202static char *strhwerrcause(uint16_t hwerrcause)
203{
204 switch (hwerrcause) {
205 case 0x02: return "system mmr error";
206 case 0x03: return "external memory addressing error";
207 case 0x12: return "performance monitor overflow";
208 case 0x18: return "raise 5 instruction";
209 default: return "undef";
210 }
211}
212
213static char *strexcause(uint16_t excause)
214{
215 switch (excause) {
216 case 0x00 ... 0xf: return "custom exception";
217 case 0x10: return "single step";
218 case 0x11: return "trace buffer full";
219 case 0x21: return "undef inst";
220 case 0x22: return "illegal inst";
221 case 0x23: return "dcplb prot violation";
222 case 0x24: return "misaligned data";
223 case 0x25: return "unrecoverable event";
224 case 0x26: return "dcplb miss";
225 case 0x27: return "multiple dcplb hit";
226 case 0x28: return "emulation watchpoint";
227 case 0x2a: return "misaligned inst";
228 case 0x2b: return "icplb prot violation";
229 case 0x2c: return "icplb miss";
230 case 0x2d: return "multiple icplb hit";
231 case 0x2e: return "illegal use of supervisor resource";
232 default: return "undef";
233 }
234}
235
236void dump(struct pt_regs *fp)
237{
238 char buf[150];
239 int i;
240 uint16_t hwerrcause, excause;
241
242 if (!ENABLE_DUMP)
243 return;
244
245
246 fp->ipend = bfin_read_IPEND();
247
248 hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
249 excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
250
251 printf("SEQUENCER STATUS:\n");
252 printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
253 fp->seqstat, fp->ipend, fp->syscfg);
254 printf(" HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause));
255 printf(" EXCAUSE : 0x%x: %s\n", excause, strexcause(excause));
256 for (i = 6; i <= 15; ++i) {
257 if (fp->ipend & (1 << i)) {
258 decode_address(buf, bfin_read32(EVT0 + 4*i));
259 printf(" physical IVG%i asserted : %s\n", i, buf);
260 }
261 }
262 decode_address(buf, fp->rete);
263 printf(" RETE: %s\n", buf);
264 decode_address(buf, fp->retn);
265 printf(" RETN: %s\n", buf);
266 decode_address(buf, fp->retx);
267 printf(" RETX: %s\n", buf);
268 decode_address(buf, fp->rets);
269 printf(" RETS: %s\n", buf);
270
271 decode_address(buf, fp->pc);
272 printf(" RETI: %s\n", buf);
273
274 if (fp->seqstat & EXCAUSE) {
275 decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
276 printf("DCPLB_FAULT_ADDR: %s\n", buf);
277 decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
278 printf("ICPLB_FAULT_ADDR: %s\n", buf);
279 }
280
281 printf("\nPROCESSOR STATE:\n");
282 printf(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
283 fp->r0, fp->r1, fp->r2, fp->r3);
284 printf(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
285 fp->r4, fp->r5, fp->r6, fp->r7);
286 printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
287 fp->p0, fp->p1, fp->p2, fp->p3);
288 printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
289 fp->p4, fp->p5, fp->fp, (unsigned long)fp);
290 printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
291 fp->lb0, fp->lt0, fp->lc0);
292 printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
293 fp->lb1, fp->lt1, fp->lc1);
294 printf(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
295 fp->b0, fp->l0, fp->m0, fp->i0);
296 printf(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
297 fp->b1, fp->l1, fp->m1, fp->i1);
298 printf(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
299 fp->b2, fp->l2, fp->m2, fp->i2);
300 printf(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
301 fp->b3, fp->l3, fp->m3, fp->i3);
302 printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
303 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
304
305 printf("USP : %08lx ASTAT: %08lx\n",
306 fp->usp, fp->astat);
307
308 printf("\n");
309}
310
311void dump_bfin_trace_buffer(void)
312{
313 char buf[150];
314 unsigned long tflags;
315 int i = 0;
316
317 if (!ENABLE_DUMP)
318 return;
319
320 trace_buffer_save(tflags);
321
322 printf("Hardware Trace:\n");
323
324 if (bfin_read_TBUFSTAT() & TBUFCNT) {
325 for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
326 decode_address(buf, bfin_read_TBUF());
327 printf("%4i Target : %s\n", i, buf);
328 decode_address(buf, bfin_read_TBUF());
329 printf(" Source : %s\n", buf);
330 }
331 }
332
333 trace_buffer_restore(tflags);
334}
335
336void bfin_panic(struct pt_regs *regs)
337{
338 if (ENABLE_DUMP) {
339 unsigned long tflags;
340 trace_buffer_save(tflags);
341 }
342
343 puts(
344 "\n"
345 "\n"
346 "\n"
347 "Ack! Something bad happened to the Blackfin!\n"
348 "\n"
349 );
350 dump(regs);
351 dump_bfin_trace_buffer();
352 puts("\n");
353 bfin_reset_or_hang();
354}
355
