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31#include <common.h>
32#include <watchdog.h>
33#include <command.h>
34#include <asm/immap.h>
35#include <netdev.h>
36
37DECLARE_GLOBAL_DATA_PTR;
38
39#ifdef CONFIG_M5208
40int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
41{
42 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
43
44 udelay(1000);
45
46 rcm->rcr = RCM_RCR_SOFTRST;
47
48
49 return 0;
50};
51
52int checkcpu(void)
53{
54 char buf1[32], buf2[32];
55
56 printf("CPU: Freescale Coldfire MCF5208\n"
57 " CPU CLK %s MHz BUS CLK %s MHz\n",
58 strmhz(buf1, gd->cpu_clk),
59 strmhz(buf2, gd->bus_clk));
60 return 0;
61};
62
63#if defined(CONFIG_WATCHDOG)
64
65void watchdog_reset(void)
66{
67 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
68 wdt->sr = 0x5555;
69 wdt->sr = 0xAAAA;
70}
71
72int watchdog_disable(void)
73{
74 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
75
76 wdt->sr = 0x5555;
77
78 wdt->sr = 0xAAAA;
79 wdt->cr = 0;
80
81 puts("WATCHDOG:disabled\n");
82 return (0);
83}
84
85int watchdog_init(void)
86{
87 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
88
89 wdt->cr = 0;
90
91
92 wdt->mr =
93 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
94 wdt->sr = 0x5555;
95 wdt->sr = 0xAAAA;
96
97 puts("WATCHDOG:enabled\n");
98 return (0);
99}
100#endif
101#endif
102
103#ifdef CONFIG_M5271
104
105
106
107
108
109int checkcpu(void)
110{
111 char buf[32];
112 unsigned short cir;
113 unsigned short pin;
114 unsigned char prn;
115 char *cpu_model;
116
117 cir = mbar_readShort(MCF_CCM_CIR);
118 pin = cir >> MCF_CCM_CIR_PIN_LEN;
119 prn = cir & MCF_CCM_CIR_PRN_MASK;
120
121 switch (pin) {
122 case MCF_CCM_CIR_PIN_MCF5270:
123 cpu_model = "5270";
124 break;
125 case MCF_CCM_CIR_PIN_MCF5271:
126 cpu_model = "5271";
127 break;
128 default:
129 cpu_model = NULL;
130 break;
131 }
132
133 if (cpu_model)
134 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
135 cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
136 else
137 printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
138 " (PIN: 0x%x) rev. %hu, at %s MHz\n",
139 pin, prn, strmhz(buf, CONFIG_SYS_CLK));
140
141 return 0;
142}
143
144int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
145{
146 mbar_writeByte(MCF_RCM_RCR,
147 MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
148 return 0;
149};
150
151#if defined(CONFIG_WATCHDOG)
152void watchdog_reset(void)
153{
154 mbar_writeShort(MCF_WTM_WSR, 0x5555);
155 mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
156}
157
158int watchdog_disable(void)
159{
160 mbar_writeShort(MCF_WTM_WCR, 0);
161 return (0);
162}
163
164int watchdog_init(void)
165{
166 mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
167 return (0);
168}
169#endif
170
171#endif
172
173#ifdef CONFIG_M5272
174int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
175{
176 volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
177
178 wdp->wdog_wrrr = 0;
179 udelay(1000);
180
181
182 wdp->wdog_wrrr = 1;
183 while (1) ;
184
185
186 return 0;
187};
188
189int checkcpu(void)
190{
191 volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
192 uchar msk;
193 char *suf;
194
195 puts("CPU: ");
196 msk = (sysctrl->sc_dir > 28) & 0xf;
197 switch (msk) {
198 case 0x2:
199 suf = "1K75N";
200 break;
201 case 0x4:
202 suf = "3K75N";
203 break;
204 default:
205 suf = NULL;
206 printf("Freescale MCF5272 (Mask:%01x)\n", msk);
207 break;
208 }
209
210 if (suf)
211 printf("Freescale MCF5272 %s\n", suf);
212 return 0;
213};
214
215#if defined(CONFIG_WATCHDOG)
216
217void watchdog_reset(void)
218{
219 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
220 wdt->wdog_wcr = 0;
221}
222
223int watchdog_disable(void)
224{
225 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
226
227 wdt->wdog_wcr = 0;
228 wdt->wdog_wirr = 0;
229 wdt->wdog_wrrr = 0;
230
231 puts("WATCHDOG:disabled\n");
232 return (0);
233}
234
235int watchdog_init(void)
236{
237 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
238
239 wdt->wdog_wirr = 0;
240
241
242 wdt->wdog_wrrr =
243 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
244 wdt->wdog_wcr = 0;
245
246 puts("WATCHDOG:enabled\n");
247 return (0);
248}
249#endif
250
251#endif
252
253#ifdef CONFIG_M5275
254int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
255{
256 volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
257
258 udelay(1000);
259
260 rcm->rcr = RCM_RCR_SOFTRST;
261
262
263 return 0;
264};
265
266int checkcpu(void)
267{
268 char buf[32];
269
270 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
271 strmhz(buf, CONFIG_SYS_CLK));
272 return 0;
273};
274
275
276#if defined(CONFIG_WATCHDOG)
277
278void watchdog_reset(void)
279{
280 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
281 wdt->wsr = 0x5555;
282 wdt->wsr = 0xAAAA;
283}
284
285int watchdog_disable(void)
286{
287 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
288
289 wdt->wsr = 0x5555;
290 wdt->wsr = 0xAAAA;
291 wdt->wcr = 0;
292
293 puts("WATCHDOG:disabled\n");
294 return (0);
295}
296
297int watchdog_init(void)
298{
299 volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
300
301 wdt->wcr = 0;
302
303
304 wdt->wmr =
305 ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
306 wdt->wsr = 0x5555;
307 wdt->wsr = 0xAAAA;
308
309 puts("WATCHDOG:enabled\n");
310 return (0);
311}
312#endif
313
314#endif
315
316#ifdef CONFIG_M5282
317int checkcpu(void)
318{
319 unsigned char resetsource = MCFRESET_RSR;
320
321 printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
322 MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
323 printf("Reset:%s%s%s%s%s%s%s\n",
324 (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
325 (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
326 (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
327 (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
328 (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
329 (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
330 (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
331 return 0;
332}
333
334int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
335{
336 MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
337 return 0;
338};
339#endif
340
341#ifdef CONFIG_M5249
342int checkcpu(void)
343{
344 char buf[32];
345
346 printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
347 strmhz(buf, CONFIG_SYS_CLK));
348 return 0;
349}
350
351int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
352{
353
354 mbar_writeByte(MCFSIM_SYPCR, 0xc0);
355 while (1) ;
356
357
358 return 0;
359};
360#endif
361
362#ifdef CONFIG_M5253
363int checkcpu(void)
364{
365 char buf[32];
366
367 unsigned char resetsource = mbar_readLong(SIM_RSR);
368 printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
369 strmhz(buf, CONFIG_SYS_CLK));
370
371 if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
372 printf("Reset:%s%s\n",
373 (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
374 : "",
375 (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
376 "");
377 }
378 return 0;
379}
380
381int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
382{
383
384 mbar_writeByte(SIM_SYPCR, 0xc0);
385 while (1) ;
386
387
388 return 0;
389};
390#endif
391
392#if defined(CONFIG_MCFFEC)
393
394
395
396
397
398int cpu_eth_init(bd_t *bis)
399{
400 return mcffec_initialize(bis);
401}
402#endif
403